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    DELTA MODULATION COMPANDER
    16.
    发明专利
    DELTA MODULATION COMPANDER 未知

    公开(公告)号：AU530585B2

    公开(公告)日：1983-07-21

    申请号：AU6321380

    申请日：1980-10-13

    Applicant: IBM

    Inventor： CROUSE WILLIAM G

    IPC: H03M3/02 ,  H03M7/34 ,  H04B14/06 ,  H03K13/22 ,  H04B12/04

    Abstract: Delay circuits (21) and (22) and logic gates (23, 24, 25) provide an output which is representative of three successive like bits appearing on the compander input line. Multiplier (26) multiplies the current delta step value DELTA by /16 and multiplier (27) multiplies the same by - /64. When the output of logic gate (25) is a 1, (three like bits), AND gate (28) let the output of multiplier (26) apply to three input adder (31). The output of this adder then delivers a delta step signal When the output of logic gate (25) is a zero, the new delta step is since AND gate (28) does not deliver any output. Multipliers (26) and (27) are shift registers, and the division by 16 or 64 is performed by achieving a four (or six) bit right shift and dropping the right most four (or six) bits.

    SPEECH DETECTOR WITH VARIABLE THRESHOLD
    17.
    发明专利
    SPEECH DETECTOR WITH VARIABLE THRESHOLD 未知

    公开(公告)号：CA1130920A

    公开(公告)日：1982-08-31

    申请号：CA343335

    申请日：1980-01-09

    Applicant: IBM

    Inventor： CROUSE WILLIAM G ,  KNOX CHARLES R

    IPC: G10L11/02 ,  G10L19/00 ,  H04B3/20 ,  H04J3/17 ,  G10L1/08

    Abstract: SPEECH DETECTOR WITH VARIABLE THRESHOLD A speech activity detection circuit and method are described in which a digitized sample of the analog speech signal in a communications system is taken n times in a period of time t. The magnitude M of each sample is calculated and the largest value of M which is encountered over a given period t is stored as a peak magnitude ?(t). This value is compared to a value ?(t-1) which is the smallest value of ?(t) from prior periods. The lesser of the two values is stored as the new value for ?(t-1). The process is continued for i periods and at the end of the ith period, the value ?(t-1) is multiplied by a constant k and the product is stored as the threshold value for the next i periods of time t. Thus, the largest signal sample magnitude over a period of time t becomes, upon multiplication by constant k, the candidate "standard" threshold level for determining whether speech exists. If this candidate is smaller than the previously stored value for a previous period of time, then the candidate becomes the new standard. In this manner, the threshold level effectively floats or varies with the conditions of the incoming signal. RA9-78-003

    OPTIMIZED DIGITAL DELTA MODULATION COMPANDER HAVING TRUNCATION EFFECT ERROR RECOVERY
    18.
    发明专利
    OPTIMIZED DIGITAL DELTA MODULATION COMPANDER HAVING TRUNCATION EFFECT ERROR RECOVERY 未知

    公开(公告)号：CA1127309A

    公开(公告)日：1982-07-06

    申请号：CA362763

    申请日：1980-10-20

    Applicant: IBM

    Inventor： CROUSE WILLIAM G

    IPC: H03M3/02 ,  H03M7/34 ,  H04B14/06 ,  H03K13/22

    Abstract: AN OPTIMIZED DIGITAL DELTA MODULATION COMPANDER HAVING TRUNCATION EFFECT ERROR RECOVERY A digital delta modulation compander circuit makes advantageous use of the mathematical truncation created during the computation of step sizes to create a nonlinear step size variation which differs from the optimum desired step size but causes convergence recovery during error conditions. It has been discovered that the truncation involved in the inaccurate approximation of mathematical calculation of the step sizes produces an advantageous result which leads to an optimized digital delta modulation compander that will recover from transmission errors over a wider range and with greater efficiency than other methods. RA9-79-004

    MULTI-MEDIA SIGNAL PROCESSOR COMPUTER SYSTEM
    20.
    发明专利
    MULTI-MEDIA SIGNAL PROCESSOR COMPUTER SYSTEM 未知

    公开(公告)号：SK31194A3

    公开(公告)日：1994-07-06

    申请号：SK31194

    申请日：1992-08-26

    Applicant: IBM

    Inventor： CARMON DONALD E ,  CROUSE WILLIAM G ,  WARE MALCOLM S

    IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10

    Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

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