公开(公告)号：JP2006197795A

公开(公告)日：2006-07-27

申请号：JP2006001813

申请日：2006-01-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DESAI DHRUV M ,  GRUENDLER NICKOLAS J ,  MORRELL CARL A ,  SHIPPY GARY R ,  SCOLLARD MICHAEL L ,  STEINMETZ MICHAEL J ,  WARE MALCOLM S ,  WOOD CHRISTOPHER L

IPC: H02J1/00 ,  G01R22/00

CPC classification number: G01V3/08 ,  G06F1/28 ,  G06F1/3203

Abstract: PROBLEM TO BE SOLVED: To provide a method, a system and an adjustment technology adapted to global system power consumption and power dissipation limit, and responsively controlling power extending over a plurality of time frames. SOLUTION: Power outputs from one or more system power supplies are measured and processed so as to generate power values in a plurality of the different time frames. Measurement values, from the different time frames, are used so as to determine whether the power consumption has to be adjusted in the system. Power from one or more apparatuses is saved, in response to the determination, and the determination compares the maximum threshold, the minimum threshold or both sets with the measured values from the different time frames. The adjustment techniques use a high-precision resistor and a voltage reference controlled current source, and derives voltage drop from the input of a sensing resistor in the power supply; and a common mode voltage is adjusted at a power supply output. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供适用于全球系统功耗和功率耗散极限的方法，系统和调整技术，以及响应地控制在多个时间帧上延伸的功率。 解决方案：测量和处理来自一个或多个系统电源的功率输出，以产生多个不同时间帧中的功率值。 使用来自不同时间帧的测量值来确定系统中是否必须调整功耗。 响应于该确定，保存来自一个或多个装置的电力，并且确定将最大阈值，最小阈值或两组与来自不同时间帧的测量值进行比较。 调节技术使用高精度电阻和参考电压源，并从电源中的感测电阻的输入端导出电压降; 并且在电源输出端调节共模电压。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：SK31194A3

公开(公告)日：1994-07-06

申请号：SK31194

申请日：1992-08-26

Applicant: IBM

Inventor： CARMON DONALD E ,  CROUSE WILLIAM G ,  WARE MALCOLM S

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

公开(公告)号：PL170083B1

公开(公告)日：1996-10-31

申请号：PL30268292

申请日：1992-08-26

Applicant: IBM

Inventor： CARMON DONALD E ,  CROUSE WILLIAM G ,  WARE MALCOLM S

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10 ,  G06F15/163

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

公开(公告)号：BR9203427A

公开(公告)日：1993-04-20

申请号：BR9203427

申请日：1992-09-02

Applicant: IBM

Inventor： CARMON DONALD E ,  CROUSE WILLIAM G ,  WARE MALCOLM S

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10 ,  G06F13/14

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

公开(公告)号：CA2069711A1

公开(公告)日：1993-03-19

申请号：CA2069711

申请日：1992-05-27

Applicant: IBM

Inventor： CARMON DONALD E ,  CROUSE WILLIAM G ,  WARE MALCOLM S

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.