公开(公告)号：WO2011031512A3

公开(公告)日：2011-06-23

申请号：PCT/US2010046742

申请日：2010-08-26

Applicant: IBM ,  BOOTH JR ROGER A ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG

Inventor： BOOTH JR ROGER A ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG

IPC: H01L27/108 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/02

CPC classification number: H01L28/90 ,  H01L23/5223 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.

Abstract translation: 叉指结构可以包括至少一个第一金属线，平行于至少一个第一金属线并与至少一个第一金属线分离的至少一个第二金属线，以及接触该至少一个第一金属线的端部的第三金属线 第一金属线并与所述至少一个第二金属线分离。 所述至少一个第一金属线不垂直接触任何金属通孔，并且至少一个第二金属线可垂直接触至少一个金属通孔。 多层交错结构可以垂直堆叠。 替代地，叉指结构可以包括多个第一金属线和多个第二金属线，每条金属线不垂直地接触任何金属通孔。 交叉结构的多个实例可以横向复制和邻接，具有或不具有旋转和/或垂直堆叠以形成电容器。

公开(公告)号：WO2006088709A2

公开(公告)日：2006-08-24

申请号：PCT/US2006004436

申请日：2006-02-08

Applicant: IBM ,  CHINTHAKINDI ANIL K ,  ESHUN EBENEZER E

Inventor： CHINTHAKINDI ANIL K ,  ESHUN EBENEZER E

IPC: H01C1/012

CPC classification number: H01L28/24 ,  H01C7/006 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin film resistor device and method of manufacture includes a layer of a thin film conductor material (20) and a current density enhancing layer (CDEL). The CDEL is an insulator material adapted to adhere to the thin film conductor material (20) and enables the said thin film resistor to carry higher current densities with reduced shift in resistance. In one embodiment, the thin film resistor device includes a single CDEL layer (50) formed on one side (atop or underneath) the thin film conductor material (20). In a second embodiment, two CDEL layers are formed on both sides (atop and underneath) of the thin film conductor material (20). The resistor device may be manufactured as part of both BEOL and FEOL rocesses.

Abstract translation: 薄膜电阻器件及其制造方法包括薄膜导体材料层（20）和电流密度增强层（CDEL）。 CDEL是适于粘附到薄膜导体材料（20）的绝缘体材料，并使所述薄膜电阻器能够承受更高的电流密度，同时具有减小的电阻偏移。 在一个实施例中，薄膜电阻器件包括在薄膜导体材料（20）的一侧（顶上或下面）形成的单个CDEL层（50）。 在第二实施例中，在薄膜导体材料（20）的两侧（顶上和下面）形成两个CDEL层。 电阻器件可以作为BEOL和FEOL处理的一部分来制造。

公开(公告)号：WO2005122245A2

公开(公告)日：2005-12-22

申请号：PCT/US2005018521

申请日：2005-05-26

Applicant: IBM ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  FEILCHENFELD NATALIE ,  GAUTSCH MICHAEL L ,  HE ZHONG-XIANG ,  MOON MATTHEW D ,  RAMACHANDRAN VIDHYA ,  WATERHOUSE BARBARA

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  FEILCHENFELD NATALIE ,  GAUTSCH MICHAEL L ,  HE ZHONG-XIANG ,  MOON MATTHEW D ,  RAMACHANDRAN VIDHYA ,  WATERHOUSE BARBARA

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/8242 ,  H01L27/01 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer (102, 106) is formed above a lower conductor layer (100) and an upper conductor layer (104, 108) is formed above the dielectric layer. The invention then forms an etch stop layer (200) above the upper conductor layer and the dielectric layer, and forms a hardmask (202) (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist (300) is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

Abstract translation: 公开了一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法。 在该方法中，在下导体层（100）的上方形成介电层（102,106），在电介质层的上方形成上导体层（104,108）。 然后，本发明在上导体层和电介质层之上形成蚀刻停止层（200），并在蚀刻停止层上形成硬掩模（202）（氧化硅硬掩模，氮化硅硬掩模等）。 接下来，在硬掩模上图案化光致抗蚀剂（300），其允许通过光刻胶蚀刻硬掩模，蚀刻停止层，电介质层和下导体层。

公开(公告)号：GB2485693B

公开(公告)日：2014-05-28

申请号：GB201201195

申请日：2010-08-26

Applicant: IBM

Inventor： BOOTH ROGER A JR ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG

IPC: H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

Abstract: An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.

公开(公告)号：GB2485693A

公开(公告)日：2012-05-23

申请号：GB201201195

申请日：2010-08-26

Applicant: IBM

Inventor： BOOTH ROGER A JR ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG

IPC: H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

Abstract: An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.