公开(公告)号：WO2009140052A3

公开(公告)日：2010-01-21

申请号：PCT/US2009041861

申请日：2009-04-28

Applicant: IBM ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

Inventor： ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

IPC: H01L21/335

CPC classification number: H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

Abstract translation: 半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成 部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。 场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。 熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料 栅电极。

公开(公告)号：WO2009003012A1

公开(公告)日：2008-12-31

申请号：PCT/US2008/068139

申请日：2008-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ESHUN, Ebenezer, E. ,  JOHNSON, Jeffrey, B. ,  PHELPS, Richard, A. ,  RASSEL, Robert, M. ,  ZIERAK, Michael, L.

Inventor： ESHUN, Ebenezer, E. ,  JOHNSON, Jeffrey, B. ,  PHELPS, Richard, A. ,  RASSEL, Robert, M. ,  ZIERAK, Michael, L.

IPC: H01L29/80 ,  H01L21/338 ,  H01L29/812

CPC classification number: H01L29/808 ,  H01L27/0617 ,  H01L27/098 ,  H01L29/36 ,  H01L29/66901

Abstract: A junction field effect transistor (JFET) (Fig. 4) has a hyperabrupl junction laj cr (54) that functions as a channel of a JFFT. The hyperabrupt junction layer (54) is formed by two dopant profiles (50. 52) of opposite t}pes such that one dopant concentration profile has a peak concentration depth at a tail end of the other dopant profile. The voltage bias to the channel is provided by a body ( 16) that is doped with the same type of dopants as the gate. This is in contrast with conventional JI7KTs that have a body that is doped with the opposite conductivity type as the gate. The body ( 16) may be electrically decoupled from (Figure 4, 10 and 30) the substrate by another reverse bias junction formed either between the body and the substrate or between a buried conductor layer beneath the body and the substrate (Figure 8. 16 and 1 10). The capability to form a thin hyperabrupt junction layer (54) allows formation of a JFET in a semiconductor-on-insulator substrate (Figure 11. 210. 230).

Abstract translation: 结型场效应晶体管（JFET）（图4）具有作为JFFT通道发挥功能的超级联结结点laj cr（54）。 超破裂结层（54）由相对的t} pes的两个掺杂剂轮廓（50.52）形成，使得一个掺杂剂浓度分布在另一个掺杂剂分布的尾端处具有峰值浓度深度。 通道的电压偏置由掺杂有与栅极相同类型的掺杂剂的体（16）提供。 这与传统的JI7KT相反，传统的JI7KT具有以与栅极相反的导电类型掺杂的主体。 主体（16）可以通过在主体和衬底之间形成的另一个反向偏置连接点或者在主体和衬底之间的掩埋导体层之间（图8,10和30）与衬底电气去耦合（图8,10和30） 和110）。 形成薄的超破坏结层（54）的能力允许在绝缘体上半导体衬底中形成JFET（图11,210,230）。

公开(公告)号：WO2005034201A2

公开(公告)日：2005-04-14

申请号：PCT/US2004/032405

申请日：2004-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  COOLBAUGH, Douglas, D. ,  ESHUN, Ebenezer, E. ,  GAMBINO, Jeffrey, P. ,  HE, Zhong-Xiang ,  RAMACHANDRAN, Vidhya

Inventor： COOLBAUGH, Douglas, D. ,  ESHUN, Ebenezer, E. ,  GAMBINO, Jeffrey, P. ,  HE, Zhong-Xiang ,  RAMACHANDRAN, Vidhya

IPC: H01L

CPC classification number: H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

Abstract translation: 一种MIM电容器的方法和结构，该结构包括：电子器件，包括：形成在半导体衬底上的层间电介质层; 形成在所述层间电介质层中的铜底电极，所述底电极共平面的顶面与所述层间电介质层的顶面形成; 与底部电极的顶表面直接接触的导电扩散阻挡层; 与所述导电扩散阻挡层的顶表面直接接触的MIM电介质; 以及与MIM电介质的顶表面直接接触的顶部电极。 导电扩散阻挡层可以凹进到铜底电极或设置的另外的凹入的导电扩散阻挡层中。 还公开了兼容的电阻器和对准标记结构。

公开(公告)号：WO2005034201A3

公开(公告)日：2007-12-06

申请号：PCT/US2004032405

申请日：2004-09-30

Applicant: IBM ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  RAMACHANDRAN VIDHYA

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  RAMACHANDRAN VIDHYA

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interievel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interievel dielectric layer, atop surface of the bottom electrode co-planer with a top surface of the interievel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

Abstract translation: 一种MIM电容器的方法和结构，所述结构包括：电子器件，包括：形成在半导体衬底上的电介质层; 形成在所述层间电介质层中的铜底电极，所述底电极共平面的顶表面具有所述电介质层的顶表面; 与底部电极的顶表面直接接触的导电扩散阻挡层; 与所述导电扩散阻挡层的顶表面直接接触的MIM电介质; 以及与MIM电介质的顶表面直接接触的顶部电极。 导电扩散阻挡层可以凹进到铜底电极或设置的另外的凹入的导电扩散阻挡层中。 还公开了兼容的电阻器和对准标记结构。

公开(公告)号：WO2006088709A3

公开(公告)日：2006-08-24

申请号：PCT/US2006/004436

申请日：2006-02-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CHINTHAKINDI, Anil, K. ,  ESHUN, Ebenezer, E.

Inventor： CHINTHAKINDI, Anil, K. ,  ESHUN, Ebenezer, E.

IPC: H01C1/012

Abstract: A thin film resistor device and method of manufacture includes a layer of a thin film conductor material (20) and a current density enhancing layer (CDEL). The CDEL is an insulator material adapted to adhere to the thin film conductor material (20) and enables the said thin film resistor to carry higher current densities with reduced shift in resistance. In one embodiment, the thin film resistor device includes a single CDEL layer (50) formed on one side (atop or underneath) the thin film conductor material (20). In a second embodiment, two CDEL layers are formed on both sides (atop and underneath) of the thin film conductor material (20). The resistor device may be manufactured as part of both BEOL and FEOL rocesses.

公开(公告)号：WO2005122245A3

公开(公告)日：2005-12-22

申请号：PCT/US2005/018521

申请日：2005-05-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  COOLBAUGH, Douglas, D. ,  ESHUN, Ebenezer, E. ,  FEILCHENFELD, Natalie ,  GAUTSCH, Michael, L. ,  HE, Zhong-Xiang ,  MOON, Matthew, D. ,  RAMACHANDRAN, Vidhya ,  WATERHOUSE, Barbara

Inventor： COOLBAUGH, Douglas, D. ,  ESHUN, Ebenezer, E. ,  FEILCHENFELD, Natalie ,  GAUTSCH, Michael, L. ,  HE, Zhong-Xiang ,  MOON, Matthew, D. ,  RAMACHANDRAN, Vidhya ,  WATERHOUSE, Barbara

IPC: G03F7/00 ,  H01L21/20 ,  H01L21/8242

Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer (102, 106) is formed above a lower conductor layer (100) and an upper conductor layer (104, 108) is formed above the dielectric layer. The invention then forms an etch stop layer (200) above the upper conductor layer and the dielectric layer, and forms a hardmask (202) (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist (300) is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

公开(公告)号：WO2011031512A3

公开(公告)日：2011-06-23

申请号：PCT/US2010046742

申请日：2010-08-26

Applicant: IBM ,  BOOTH JR ROGER A ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG

Inventor： BOOTH JR ROGER A ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG

IPC: H01L27/108 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/02

CPC classification number: H01L28/90 ,  H01L23/5223 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.

Abstract translation: 叉指结构可以包括至少一个第一金属线，平行于至少一个第一金属线并与至少一个第一金属线分离的至少一个第二金属线，以及接触该至少一个第一金属线的端部的第三金属线 第一金属线并与所述至少一个第二金属线分离。 所述至少一个第一金属线不垂直接触任何金属通孔，并且至少一个第二金属线可垂直接触至少一个金属通孔。 多层交错结构可以垂直堆叠。 替代地，叉指结构可以包括多个第一金属线和多个第二金属线，每条金属线不垂直地接触任何金属通孔。 交叉结构的多个实例可以横向复制和邻接，具有或不具有旋转和/或垂直堆叠以形成电容器。

公开(公告)号：WO2011031512A2

公开(公告)日：2011-03-17

申请号：PCT/US2010/046742

申请日：2010-08-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BOOTH, Jr., Roger A ,  COOLBAUGH, Douglas D ,  ESHUN, Ebenezer E ,  HE, Zhong-Xiang

Inventor： BOOTH, Jr., Roger A ,  COOLBAUGH, Douglas D ,  ESHUN, Ebenezer E ,  HE, Zhong-Xiang

IPC: H01L27/108 ,  H01L21/8242 ,  H01L21/768 ,  H01L21/3205 ,  H01L27/02

CPC classification number: H01L28/90 ,  H01L23/5223 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.

Abstract translation: 指叉结构可以包括至少一个第一金属线，与所述至少一个第一金属线平行且与所述至少一个第一金属线分离的至少一个第二金属线，以及第三金属 所述至少一条第一金属线的线接触端与所述至少一条第二金属线分离。 所述至少一个第一金属线不垂直接触任何金属通孔，并且至少一个第二金属线可垂直接触至少一个金属通孔。 多层交叉指型结构可以垂直堆叠。 可选地，交叉指型结构可以包括多条第一金属线和多条第二金属线，每条金属线不垂直接触任何金属通孔。 叉指结构的多个实例可以横向复制和邻接，有或没有旋转，和/或垂直堆叠以形成电容器。

公开(公告)号：WO2009140052A2

公开(公告)日：2009-11-19

申请号：PCT/US2009/041861

申请日：2009-04-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ESHUN, Ebenezer, E. ,  HE, Zhong-xiang ,  RASSEL, Robert, M. ,  COOLBAUGH, Douglas ,  GEBRESELASIE, Ephrem, G. ,  WANG, Ping-chuan ,  KIM, Deok-kee ,  KOTHANDARAMAN, Chandrasekharan ,  ROBSON, Norman, W. ,  MOY, Dan ,  SAFRAN, John, M. ,  STEIN, Kenneth, J. ,  HO, Herbert, L. ,  YAN, Hongwen

Inventor： ESHUN, Ebenezer, E. ,  HE, Zhong-xiang ,  RASSEL, Robert, M. ,  COOLBAUGH, Douglas ,  GEBRESELASIE, Ephrem, G. ,  WANG, Ping-chuan ,  KIM, Deok-kee ,  KOTHANDARAMAN, Chandrasekharan ,  ROBSON, Norman, W. ,  MOY, Dan ,  SAFRAN, John, M. ,  STEIN, Kenneth, J. ,  HO, Herbert, L. ,  YAN, Hongwen

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

Abstract translation: 半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成 部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。 场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。 熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料 栅电极。

公开(公告)号：WO2006088709A2

公开(公告)日：2006-08-24

申请号：PCT/US2006004436

申请日：2006-02-08

Applicant: IBM ,  CHINTHAKINDI ANIL K ,  ESHUN EBENEZER E

Inventor： CHINTHAKINDI ANIL K ,  ESHUN EBENEZER E

IPC: H01C1/012

CPC classification number: H01L28/24 ,  H01C7/006 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin film resistor device and method of manufacture includes a layer of a thin film conductor material (20) and a current density enhancing layer (CDEL). The CDEL is an insulator material adapted to adhere to the thin film conductor material (20) and enables the said thin film resistor to carry higher current densities with reduced shift in resistance. In one embodiment, the thin film resistor device includes a single CDEL layer (50) formed on one side (atop or underneath) the thin film conductor material (20). In a second embodiment, two CDEL layers are formed on both sides (atop and underneath) of the thin film conductor material (20). The resistor device may be manufactured as part of both BEOL and FEOL rocesses.

Abstract translation: 薄膜电阻器件及其制造方法包括薄膜导体材料层（20）和电流密度增强层（CDEL）。 CDEL是适于粘附到薄膜导体材料（20）的绝缘体材料，并使所述薄膜电阻器能够承受更高的电流密度，同时具有减小的电阻偏移。 在一个实施例中，薄膜电阻器件包括在薄膜导体材料（20）的一侧（顶上或下面）形成的单个CDEL层（50）。 在第二实施例中，在薄膜导体材料（20）的两侧（顶上和下面）形成两个CDEL层。 电阻器件可以作为BEOL和FEOL处理的一部分来制造。