公开(公告)号：AU2020233909B2

公开(公告)日：2023-04-13

申请号：AU2020233909

申请日：2020-02-28

Applicant: IBM

Inventor： JAVADIABHARI ALI ,  GAMBETTA JAY MICHAEL ,  FARO SERTAGE ISMAEL ,  NATION PAUL

IPC: G06N10/00

Abstract: A method for validation and runtime estimation of a quantum algorithm includes receiving a quantum algorithm and simulating the quantum algorithm, the quantum algorithm forming a set of quantum gates. The method further includes analyzing a first set of parameters of the set of quantum gates and analyzing a second set of parameters of a set of qubits performing the set of quantum gates. The method further includes transforming, in response to determining at least one of the first set of parameters or the second set of parameters meets an acceptability criterion, the quantum algorithm into a second set of quantum gates.

公开(公告)号：AU2020262057A1

公开(公告)日：2021-09-30

申请号：AU2020262057

申请日：2020-03-27

Applicant: IBM

Inventor： CROSS ANDREW ,  CHAMBERLAND CHRISTOPHER ,  GAMBETTA JAY MICHAEL ,  HERTZBERG JARED ,  YODER THEODORE ,  ZHU GUANYU

IPC: G06N10/00

Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.

公开(公告)号：CA3137264A1

公开(公告)日：2020-10-29

申请号：CA3137264

申请日：2020-03-27

Applicant: IBM

Inventor： CROSS ANDREW ,  CHAMBERLAND CHRISTOPHER ,  GAMBETTA JAY MICHAEL ,  HERTZBERG JARED ,  YODER THEODORE ,  ZHU GUANYU

Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.