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公开(公告)号：AU2021290959A1
公开(公告)日：2022-11-10
申请号：AU2021290959
申请日：2021-06-15
Applicant: IBM
Inventor： GUMANN PATRYK , CROSS ANDREW , HART SEAN , GAMBETTA JAY
Abstract: A quantum system includes a qubit array comprising a plurality of qubits. A bus resonator is coupled between at least one pair of qubits in the qubit array. A switch is coupled between the at least one qubit pair of qubits.
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公开(公告)号：IL287253D0
公开(公告)日：2021-12-01
申请号：IL28725321
申请日：2021-10-13
Applicant: IBM , CROSS ANDREW , CHAMBERLAND CHRISTOPHER , GAMBETTA JAY MICHAEL , HERTZBERG JARED , YODER THEODORE , ZHU GUANYU
Inventor： CROSS ANDREW , CHAMBERLAND CHRISTOPHER , GAMBETTA JAY MICHAEL , HERTZBERG JARED , YODER THEODORE , ZHU GUANYU
Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.
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公开(公告)号：DE112017007772T5
公开(公告)日：2020-04-16
申请号：DE112017007772
申请日：2017-12-06
Applicant: IBM
Inventor： CROSS ANDREW , BISHOP LEV SAMUEL , SERTAGE ISMAEL FARO , GAMBETTA JAY
Abstract: Eine Kompatibilität zwischen einer Konfiguration eines Quantenprozessors (q-Prozessor) eines Quanten-Cloud-Rechenknotens (Quantum Cloud Compute Node, QCCN) in einer Quanten-Cloud-Umgebung (Quantum Cloud Environment, QCE) und einer Operation wird festgestellt, die in einer ersten Anweisung in einem Abschnitt (q-Abschnitt) eines Jobs angefordert wird, der an die QCE übergeben wird, wobei die QCE den QCCN und einen herkömmlichen Rechenknoten (Conventional Compute Node, CCN) enthält, wobei der CCN einen herkömmlichen Prozessor enthält, der für binäre Berechnungen konfiguriert ist. Als Reaktion auf das Feststellen wird eine Quantenanweisung (q-Anweisung) erzeugt, die der ersten Anweisung entspricht. Die q-Anweisung wird unter Verwendung des q-Prozessors des QCCN ausgeführt, um ein Quantenausgabesignal (q-Signal) zu erzeugen. Das q-Signal wird in ein entsprechendes Quanten-Computing-Resultat (q-Resultat) umgewandelt. Ein endgültiges Resultat wird an ein Übergabesystem zurückgegeben, das den Job übergeben hat, wobei das endgültige Resultat das q-Resultat aufweist.
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公开(公告)号：AU2021402531B2
公开(公告)日：2024-08-08
申请号：AU2021402531
申请日：2021-12-13
Applicant: IBM
Inventor： ZHU GUANYU , CROSS ANDREW
IPC: G06N10/70
Abstract: Systems, computer-implemented methods, and computer program products to facilitate logical Hadamard gate operation and gauge fixing in subsystem codes are provided. According to an embodiment, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components can comprise a gauge fixing component that applies a gauge fixing operation to a subsystem code of an encoded qubit to generate a switched subsystem code. The computer executable components can further comprise a transverse component that applies a transversal Hadamard operation to the switched subsystem code to generate a rotated subsystem code.
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公开(公告)号：BR112021021332A2
公开(公告)日：2022-01-18
申请号：BR112021021332
申请日：2020-03-27
Applicant: IBM
Inventor： CROSS ANDREW , CHAMBERLAND CHRISTOPHER , ZHU GUANYU , HERTZBERG JARED , JAY MICHAEL GAMBETTA , YODER THEODORE
IPC: G06N10/00
Abstract: código quântico para redução de colisões de frequência em treliças de qubit. um computador quântico inclui um processador quântico que inclui uma primeira pluralidade de qubits dispostos em um padrão de treliça hexagonal de tal forma que cada um está substancialmente localizado em um ápice hexágono, e uma segunda pluralidade de qubits cada um disposto substancialmente ao longo de uma borda hexagona. cada uma das primeiras pluralidades de qubits é acoplado a três qubits vizinhos mais próximos da segunda pluralidade de qubits, e cada uma da segunda pluralidade de qubits é acoplado a dois qubits vizinhos mais próximos da primeira pluralidade de qubits. cada uma das segundas pluralidades de qubits é um qubit de controle em uma frequência de controle. cada uma das primeiras pluralidades de qubits é um qubit alvo em uma das primeiras frequências de alvo ou uma segunda frequência de alvo. o computador quântico inclui um dispositivo de correção de erros configurado para operar no padrão de treliça hexagonal da pluralidade de qubits, de modo a detectar e corrigir erros de dados.
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Patent Agency Ranking
公开(公告)号：CA3176185A1
公开(公告)日：2021-12-23
申请号：CA3176185
申请日：2021-06-15
Applicant: IBM
Inventor： GUMANN PATRYK , CROSS ANDREW , HART SEAN , GAMBETTA JAY
Abstract: A quantum system includes a qubit array comprising a plurality of qubits. A bus resonator is coupled between at least one pair of qubits in the qubit array. A switch is coupled between the at least one qubit pair of qubits.
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公开(公告)号：SG11202109842YA
公开(公告)日：2021-10-28
申请号：SG11202109842Y
申请日：2020-03-27
Applicant: IBM
Inventor： CROSS ANDREW , CHAMBERLAND CHRISTOPHER , GAMBETTA JAY , HERTZBERG JARED , YODER THEODORE , ZHU GUANYU
IPC: G06N10/00
Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.
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公开(公告)号：MX391726B
公开(公告)日：2025-03-21
申请号：MX2021012893
申请日：2021-10-21
Applicant: IBM
Inventor： CROSS ANDREW , CHAMBERLAND CHRISTOPHER , ZHU GUANYU , HERTZBERG JARED , GAMBETTA JAY MICHAEL , YODER THEODORE
Abstract: Una computadora cuántica incluye un procesador cuántico que incluye una primera pluralidad de bits cuánticos arreglados en un patrón de cuadrícula hexagonal tal que cada uno se ubique sustancialmente en un ápice de hexágono, y una segunda pluralidad de bits cuánticos cada uno arreglado sustancialmente a lo largo de un borde de hexágono. Cada una de la primera pluralidad de bits cuánticos se acopla a tres bits cuánticos vecinos más cercanos de la segunda pluralidad de bits cuánticos, y cada una de la segunda pluralidad de bits cuánticos se acopla a dos bits cuánticos vecinos más cercanos de la primera pluralidad de bits cuánticos. Cada uno de la segunda pluralidad de bits cuánticos es un bit cuántico de control a una frecuencia de control. Cada uno de la primera pluralidad de bits cuánticos es un bit cuántico diana en una de una primera frecuencia diana o una segunda frecuencia diana. La computadora cuántica incluye un dispositivo de corrección de errores configurado para operar en el patrón de cuadrícula hexagonal de la pluralidad de bits cuánticos a fin de detectar y corregir errores de datos.
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公开(公告)号：AU2020262057A1
公开(公告)日：2021-09-30
申请号：AU2020262057
申请日：2020-03-27
Applicant: IBM
Inventor： CROSS ANDREW , CHAMBERLAND CHRISTOPHER , GAMBETTA JAY MICHAEL , HERTZBERG JARED , YODER THEODORE , ZHU GUANYU
IPC: G06N10/00
Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.
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公开(公告)号：CA3137264A1
公开(公告)日：2020-10-29
申请号：CA3137264
申请日：2020-03-27
Applicant: IBM
Inventor： CROSS ANDREW , CHAMBERLAND CHRISTOPHER , GAMBETTA JAY MICHAEL , HERTZBERG JARED , YODER THEODORE , ZHU GUANYU
Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.
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