STORAGE SUBSYSTEM INCLUDING A BYPASSABLE CACHE

    公开(公告)号:DE3278651D1

    公开(公告)日:1988-07-14

    申请号:DE3278651

    申请日:1982-08-25

    Applicant: IBM

    Abstract: A storage subsystem hierarchy has a caching buffer (15) and a backing store (14); the backing store preferably having a disk-type data-storage apparatus. A directory indicates data stored in the caching buffer. Upon a data-storage access, read or write, within a series of such accesses, resulting in a cache miss, all subsequent data storage accesses in the series are made to the the backing store to the exclusion of the caching buffer even though the caching buffer has storage space allocated for such a data transfer. Selected limits are placed on the series to the backing store, such as receiving on end of series (end of command chain) indication from a using unit, crossing DASD cylinder boundaries, receiving an out of bounds address or receiving certain device oriented commands.

    14.
    发明专利
    未知

    公开(公告)号:DE69312781D1

    公开(公告)日:1997-09-11

    申请号:DE69312781

    申请日:1993-04-13

    Applicant: IBM

    Abstract: A method and system disclosed for enhanced efficiency of backup copying of designated datasets stored within storage devices (61) coupled to the data processing system via a storage control unit (65) having memory (66) therein. Application execution is temporarily suspended to form a dataset logical-to-physical address concordance to be utilized to administer backup copying. Application initiated updates to uncopied portions of the designated datasets are temporarily deferred until sidefiles of the affected portions are written to memory (66). Portions of the designated datasets are then accessed and copied utilizing selected data retrieval command sequences. A sidefile status query is appended to said command sequences and the presence of data within memory (66) is determined. The sidefiles are then accessed and copied to alternate storage locations in a backup copy order defined by the address concordance.

    18.
    发明专利
    未知

    公开(公告)号:DE69204143T2

    公开(公告)日:1996-05-02

    申请号:DE69204143

    申请日:1992-11-13

    Applicant: IBM

    Abstract: Combination of split memory modules, each module partitioned into a first section and a second section. Each module has its own power source (101, 103) so that the failure of a single power source will not affect the other modules. A particular block of data is not stored in both sections of a single module. Each modified block of data is stored in the first section of one module and the second section of a different module. Failure of a power supply will not cause a loss in data since the modified data is also stored in a section of a module not powered by the same power supply. The failure of all power supplies will not result in the loss of any data if either the first or second section of the memory modules is non-volatile, i.e., backed up, usually by battery sources.

    Roll mode for cached data storage
    19.
    发明专利

    公开(公告)号:HK138594A

    公开(公告)日:1994-12-16

    申请号:HK138594

    申请日:1994-12-08

    Applicant: IBM

    Abstract: A so-called "roll mode" technique provides block transfer with a disk-type of direct-access data-storage device (DASD). A set of chained commands for accessing record areas enables rapidly accessing a plurality of records within a given DASD cylinder of tracks. The rotational position of the surfaces is checked. The command within the chain, irrespective of its location, having the closest logical rotational proximity to the instant rotational position of the surfaces is selected as the first command in the chain. The chain is executed beginning at the indicated rotational position selected command through the end of the chain and then wrapped to the beginning of the original chain and continuing on until the command immediately preceding the rotational position selected command has been executed.

    PERIPHERAL STORAGE SYSTEM HAVING MULTIPLE DATA TRANSFER RATES

    公开(公告)号:DE3380502D1

    公开(公告)日:1989-10-05

    申请号:DE3380502

    申请日:1983-09-20

    Applicant: IBM

    Abstract: Fast and slow channels (13, 14) are attached to a cached peripheral storage system, having a front store (40) and a backing store (16) preferably with a plurality of data storage devices. The peripheral data storage device (16) data transfer rate is not greater than the data rate of the fast channels but greater than the data rate of the slow channels. For data associated with a fast channel, data promotion from the backing store to the front store is designed to encourage read hits while discouraging write hits. For the slow channel, all data goes through the front store. Cache bypassing controls (61) are handled through the LRU (least recently used) replacement algorithm (43) for the slow channels. A common demotion of data from the front store to the backing store is used for all channels. Front store occupancy varies in that buffering for slow channels (data rate change) tends to store and keep full tracks, while caching for fast channels limits data occupancy. For a fast channel, a cache miss results in directly accessing the backing store. The data storage devices are preferably disk data storage devices (DASD) or magnetic tape recorders.

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