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    3.
    发明专利
    未知

    公开(公告)号：DE3851730T2

    公开(公告)日：1995-05-04

    申请号：DE3851730

    申请日：1988-06-10

    Applicant: IBM

    Inventor： TAYLER GERALD ELLSWORTH ,  WAGNER ROBERT E

    IPC: G06F3/06 ,  G06F12/08 ,  G06F12/12

    Abstract: The disclosure relates to sequential performance of a cached data storage subsystem with a minimal control signal processing. Sequential access is first detected by monitoring and examining the quantity of data accessed per unit of data storage (track) across a set of contiguously addressable tracks. Since the occupancy of the data in the cache is usually time limited, this examination provides an indication of the rate of sequential processing for a data set, i.e., a data set is being processed usually in contiguously addressable data storage units of a data storage system. Based upon the examination of a group of the tracks in a cache, the amount of data to be promoted to the cache from a backing store in anticipation of future host processor references is optimised. A promotion factor is calculated by combining the access extents monitored in the individual data storage areas and is expressed in a number of tracks units to be promoted. The examination of the group of tracks units and the implementation of the data promotion and demotion (early cast-out) is synchronised which results in a synergistic effect for increasing throughput of the cache for sequentially-processed data. A limit of promotion is determined to create a window of sequential data processing.

    DATA PROCESSING APPARATUS INCLUDING A SELECTIVELY RESETTABLE PERIPHERAL SYSTEM
    6.
    发明专利
    DATA PROCESSING APPARATUS INCLUDING A SELECTIVELY RESETTABLE PERIPHERAL SYSTEM 未知

    公开(公告)号：DE3279221D1

    公开(公告)日：1988-12-22

    申请号：DE3279221

    申请日：1982-08-10

    Applicant: IBM

    Inventor： CHRISTIAN JOHN HUNT ,  NOLTA ARTHUR HERBERT ,  REED DAVID GORDON ,  RIECK RICHARD EDWARD ,  TAYLER GERALD ELLSWORTH ,  TRUAN TERRELL NELSON ,  WILLIAMS JOHN STEPHEN

    IPC: G06F11/14 ,  G06F12/08 ,  G06F13/00 ,  G06F13/12

    Abstract: The disclosed embodiment of a selectively resetable multiple device peripheral system, addressed logically by a host system (11), includes direct access storage devices (DASD) (18) which are connected to the host via a cache. (40). Each device can be independently addressed by any one of a plurality of addresses (16; 17), also termed logical devices and exposures (17). Since operations between DASD and cache are combined for all of the independent logical devices, resetting operations related to one independent logical device can inadvertently interfere with operations of another independent logical device. To maintain data integrity, a programmed controller accommodates logical device independence by using queues and control blocks relating to the DASD and logical devices, respectively scanning for interference of reset with non selected logical devices and forcing false completion on each such interfered with operation, including elimination from queues.

    8.
    发明专利
    未知

    公开(公告)号：DE3851730D1

    公开(公告)日：1994-11-10

    申请号：DE3851730

    申请日：1988-06-10

    Applicant: IBM

    Inventor： TAYLER GERALD ELLSWORTH ,  WAGNER ROBERT E

    IPC: G06F3/06 ,  G06F12/08 ,  G06F12/12

    Abstract: The disclosure relates to sequential performance of a cached data storage subsystem with a minimal control signal processing. Sequential access is first detected by monitoring and examining the quantity of data accessed per unit of data storage (track) across a set of contiguously addressable tracks. Since the occupancy of the data in the cache is usually time limited, this examination provides an indication of the rate of sequential processing for a data set, i.e., a data set is being processed usually in contiguously addressable data storage units of a data storage system. Based upon the examination of a group of the tracks in a cache, the amount of data to be promoted to the cache from a backing store in anticipation of future host processor references is optimised. A promotion factor is calculated by combining the access extents monitored in the individual data storage areas and is expressed in a number of tracks units to be promoted. The examination of the group of tracks units and the implementation of the data promotion and demotion (early cast-out) is synchronised which results in a synergistic effect for increasing throughput of the cache for sequentially-processed data. A limit of promotion is determined to create a window of sequential data processing.

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