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    Method of testing devices using untested devices as a reference standard
    1.
    发明授权
    Method of testing devices using untested devices as a reference standard 失效
    使用未定义的设备作为参考标准测试设备的方法

    公开(公告)号：US3636443A

    公开(公告)日：1972-01-18

    申请号：US3636443D

    申请日：1970-10-29

    Applicant: IBM

    Inventor： SINGH SHANKER ,  SINGH VIJENDRAP P

    IPC: G01R31/3193 ,  G01R15/12

    CPC classification number: G01R31/3193

    Abstract: A method of testing circuit chips using untested chips as a standard. A portion of the untested chips is selected at random and used as a reference standard. A random pulse generator generates patterns of pulses which are applied to the test standard chips and also successively to each of the remaining chips. A majority logic gate is employed to determine the majority outputs of the test standard chips. Each majority output is compared with the respective outputs of the remaining chips to determine which of the latter are qualified. Some of the qualified chips are then substituted for the test standard chips and the cycle is then repeated with the qualified chips, and repeated again with the twice-qualified chips. With each successive cycle the probability of qualifying good chips converges toward unity.

    Fast adder for multi-number additions
    2.
    发明授权
    Fast adder for multi-number additions 失效
    快速添加多个添加剂

    公开(公告)号：US3675001A

    公开(公告)日：1972-07-04

    申请号：US3675001D

    申请日：1970-12-10

    Applicant: IBM

    Inventor： SINGH SHANKER

    IPC: G06F7/50 ,  G06F7/509

    CPC classification number: G06F7/509 ,  G06F7/5045

    Abstract: A fast adder for adding more than three numbers, the digits of each of which are arranged in groups in accordance with the expression n (log2 (k-1)) where: (LOG2 (K-1) IS THE SMALLEST INTEGER GREATER OR EQUAL TO LOG2 (K1) N THE NUMBER OF DIGITS IN EACH GROUP AND K THE NUMBER OF NUMBERS TO BE ADDED. The most significant digit of each group of digits comprising each number to be added is applied to an adder which directly produces a partial sum consisting of a sum digit and carry digits. In the next cycle of operation, the second most significant digit of each group of digits is applied to the same adder to produce a corresponding partial sum in the same manner. Then, the third most significant digit of each group of digits is applied to the same adder and so on until all of the digits have been processed. Each partial sum includes a number of digits having overlapping positional significance (weight) with respect to an equal number of digits of another partial sum. However, no more than two digits possess the same positional significance. Half of the digits from all of the partial sums are applied to a first register and the remainder of the digits are applied to a second register with appropriate positional significance. One additional cycle is required in order to apply the digits in the two registers to a carry look-ahead adder to yield the desired final sum.

    Abstract translation: 一个用于加上三个数字的快速加法器，每个数字根据表达式n = [log2（k-1）]分组排列，其中：

    DUAL DATA BUFFERING IN SEPARATELY POWERED MEMORY MODULES
    4.
    发明专利
    DUAL DATA BUFFERING IN SEPARATELY POWERED MEMORY MODULES 未知

    公开(公告)号：CA2072728A1

    公开(公告)日：1993-05-21

    申请号：CA2072728

    申请日：1992-06-29

    Applicant: IBM

    Inventor： HARTUNG MICHAEL H ,  SINGH SHANKER ,  WADE FORREST L

    IPC: G06F12/08 ,  G06F1/26 ,  G06F11/20 ,  G06F12/16 ,  G11C5/14

    Abstract: TU9-91-018 DUAL DATA BUFFERING IN SEPARATELY POWERED MEMORY MODULES Combination of split memory modules, each module partitioned into a first section and a second section. Each module has its own power source so that the failure of a single power source will not affect the other modules. A particular block of data is not stored in both sections of a single module. Each block of data is stored in the first section of one module and the second section of a different module. Failure of a power supply will not cause a loss in data since the same data is stored in a section of a module not powered by the same power supply. The failure of all power supplies will not result in the loss of any data if either the first or second section of the memory modules is nonvolatile, i.e., backed up, usually by battery sources.

    5.
    发明专利
    未知

    公开(公告)号：DE3481350D1

    公开(公告)日：1990-03-15

    申请号：DE3481350

    申请日：1984-08-17

    Applicant: IBM

    Inventor： SHAH SIDDHARTH ROMESHCHANDRA ,  SINGH SHANKER ,  SINGH VIJENDRA PAL

    IPC: G06F12/16 ,  G11C29/00 ,  G06F11/00 ,  G06F11/20

    Abstract: In a reconfigurable memory a spare chip (40) is substituted for a faulty chip when an uncorrectable error condition results from an alignment of two errors in bit positions accessed through the same chip row decoder (12) while an address bit permutation apparatus (30, 32) is used to misalign faulty bits when they occur in bit positions accessed through different decoders.

    6.
    发明专利
    未知

    公开(公告)号：DE69204143D1

    公开(公告)日：1995-09-21

    申请号：DE69204143

    申请日：1992-11-13

    Applicant: IBM

    Inventor： HARTUNG MICHAEL HOWARD ,  SINGH SHANKER ,  WADE FORREST LEE

    IPC: G06F12/08 ,  G06F1/26 ,  G06F11/20 ,  G06F12/16 ,  G11C5/14

    Abstract: Combination of split memory modules, each module partitioned into a first section and a second section. Each module has its own power source (101, 103) so that the failure of a single power source will not affect the other modules. A particular block of data is not stored in both sections of a single module. Each modified block of data is stored in the first section of one module and the second section of a different module. Failure of a power supply will not cause a loss in data since the modified data is also stored in a section of a module not powered by the same power supply. The failure of all power supplies will not result in the loss of any data if either the first or second section of the memory modules is non-volatile, i.e., backed up, usually by battery sources.

    8.
    发明专利
    未知

    公开(公告)号：DE69204143T2

    公开(公告)日：1996-05-02

    申请号：DE69204143

    申请日：1992-11-13

    Applicant: IBM

    Inventor： HARTUNG MICHAEL HOWARD ,  SINGH SHANKER ,  WADE FORREST LEE

    IPC: G06F12/08 ,  G06F1/26 ,  G06F11/20 ,  G06F12/16 ,  G11C5/14

    Abstract: Combination of split memory modules, each module partitioned into a first section and a second section. Each module has its own power source (101, 103) so that the failure of a single power source will not affect the other modules. A particular block of data is not stored in both sections of a single module. Each modified block of data is stored in the first section of one module and the second section of a different module. Failure of a power supply will not cause a loss in data since the modified data is also stored in a section of a module not powered by the same power supply. The failure of all power supplies will not result in the loss of any data if either the first or second section of the memory modules is non-volatile, i.e., backed up, usually by battery sources.

    9.
    发明专利
    未知

    公开(公告)号：DE3484542D1

    公开(公告)日：1991-06-13

    申请号：DE3484542

    申请日：1984-03-09

    Applicant: IBM

    Inventor： SINGH SHANKER ,  SINGH VINJENDRA P

    IPC: G06F12/16 ,  G06F11/00 ,  G06F12/00

    Abstract: This permutation circuit can be considered to be a multibit adder without a carry. In one embodiment it takes the form of m address bits being fed to m+y 2-way exclusive OR gates (12) with m+y permutation bits to generate m+y input bits accessing a decoder (10) with 2 m output positions. In another embodimentthe decoder takes the form of an m-bit adder (14) which adds m address bits to m permutation bits to generate an m-bit actual address. Multiple decoders of both types may be joinedtogether in various combinationsto generate higher order addresses. Also, k full-adders of less than m bits can be used in similar fashion as m+y Exor gates to provide shift rotate capability within a desired block of 2 Y rows.

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