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    SINGLE ELECTRODE U-MOSFET RANDOM ACCESS MEMORY
    12.
    发明专利
    SINGLE ELECTRODE U-MOSFET RANDOM ACCESS MEMORY 未知

    公开(公告)号：CA1133136A

    公开(公告)日：1982-10-05

    申请号：CA348131

    申请日：1980-03-21

    Applicant: IBM

    Inventor： HO IRVING T ,  RISEMAN JACOB

    IPC: H01L27/10 ,  G11C11/35 ,  G11C11/404 ,  H01L21/31 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  G11C11/40

    Abstract: SINGLE ELECTRODE U-MOSFET RANDOM ACCESS MEMORY A method for making highly dense, dielectrically isolated, U-shaped MOSFET. In a preferred method a monocrystalline silicon P substrate with a N+ layer thereon, a P layer on the N+ layer and a N+ layer on the P layer is provided. A pattern of U-shaped openings is formed in the body through to the P substrate by the reactively ion etching technique. This pattern of openings is filled with an insulator material, such as silicon dioxide. A conductive layer of N+ doped polycrystalline silicon is deposited on the bare surface of this silicon body. Openings are formed in the polycrystalline silicon over the silicon dioxide filled openings. A silicon dioxide layer is then grown by, for example, thermal oxidation over the polycrystalline silicon layer. Reactively ion etching is used to produce substantially U-shaped openings through the layers over the P substrate and into the P substrate to substantially bisect the regions of monocrystalline silicon. This etching step forms two storage cells in the monocrystalline silicon areas and a bit line for each column of cells in the polycrystalline silicon FI9-78-049 layer. A silicon dioxide gate insulator is grown on the monocrystalline silicon surfaces of the Ushaped openings by thermal oxidation in a suitable ambient. Conductively doped polycrystalline silicon is deposited in the U-shaped openings over the silicon dioxide gate insulator layer until the openings are filled and cover the surface of the body. The conductively doped polycrystalline silicon on the surface of the body is etched in a suitable pattern to produce the word lines of the random access memory device. FI9-78-049

    CHARGE INJECTION TRANSISTOR MEMORY
    13.
    发明专利
    CHARGE INJECTION TRANSISTOR MEMORY 未知

    公开(公告)号：CA1097813A

    公开(公告)日：1981-03-17

    申请号：CA272249

    申请日：1977-02-21

    Applicant: IBM

    Inventor： HO IRVING T ,  RISEMAN JACOB

    IPC: G11C11/405 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/07 ,  H01L27/102 ,  H01L27/108 ,  G11C11/40 ,  H01L29/78

    Abstract: CHARGE INJECTION TRANSISTOR MEMORY Disclosed is a dynamic memory cell storing digital information, particularly adapted for integrated semiconductor circuit fabrication. The circuit configuration has a bipolar transistor with information storage preferably in the capacitance of the junctions, and a field effect transistor (FET) for selectively injecting charge into the capacitances. In integrated form, isolation is required only between columns of cells, a buried subcollector forming a common sense line for the entire column, while each of the base regions (also used as a first controlled region of the FET) requires no external contact at all. A further impurity region formed into each column of cells forms a second region of the FET and can be used as a bit line for the entire column. In one embodiment, separate contacts are provided for each of the emitter regions and each of the FET gate regions, while in another embodiment, only a single contact to both of the emitter region and FET gate region of each cell is required. FI9-75-042

    14.
    发明专利
    未知

    公开(公告)号：FR2337464A1

    公开(公告)日：1977-07-29

    申请号：FR7636402

    申请日：1976-11-29

    Applicant: IBM

    Inventor： HENLE ROBERT A ,  HO IRVING T

    IPC: H03F3/345 ,  H03F3/34 ,  H03K5/02 ,  H03K17/04 ,  H03K17/60 ,  H03K17/687 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/08 ,  H03K19/0944 ,  G11C5/00

    Abstract: An intermediate driver circuit comprising at least five stages which are cascaded between a signal driver, such as a logic circuit on an LSI chip, and a high capacity load driver, such as a driver for long off chip interconnection lines, wherein the total delay in the signal source caused by great disparity between the capacitance of the signal driver and the load driver is minimized. The delay is minimized by use of a cascaded series of n-intermediate drivers where n=1nM, AND WHERE THE CAPACITANCE OF ANY INTERMEDIATE STAGE IS CP = 2ROOT C(P-1) . C(P+1). Use of these parameters in the design of intermediate stages, each having a capacitance designed in accordance with the foregoing equations has been found to be useful in connection with amplifiers having five or more intermediate stages, and wherein the ratio of capacitance of the load circuit to the capacitance of the driver circuit is greater than about one hundred to one. The utility of these design parameters in instances where the ratio of capacitance is greater than a thousand to one, and the number of intermediate stages is ten or greater is particularly apparent.

    MODULO 9 RESIDUE GENERATING AND CHECKING CIRCUIT
    15.
    发明专利
    MODULO 9 RESIDUE GENERATING AND CHECKING CIRCUIT 未知

    公开(公告)号：CA1010572A

    公开(公告)日：1977-05-17

    申请号：CA183605

    申请日：1973-10-17

    Applicant: IBM

    Inventor： CHEN TIEN C ,  HO IRVING T

    IPC: G06F7/38 ,  G06F7/00 ,  G06F7/493 ,  G06F7/499 ,  G06F11/10

    Abstract: A modulo 9 residue generating and checking circuit for checking the accuracy of decimal addition operations in digital computers and other data processing equipment. A set of data words each representing a number to be added is transmitted to a multi-number adder which adds the words and provides a smaller set of words as a subtotal sum. The bits of the subtotal words are then divided into two groups. Each group of bits is fed to a respective modulo 9 residue generator which calculates the modulo 9 residue of the group. The two resulting residues are then fed to a third modulo 9 residue generator which calculates the modulo 9 residue of the sum of the two residues, thereby providing the modulo 9 residue of the sum of the original set of data words. This result may then be compared in the conventional manner with the modulo 9 residue of the sum resulting from the addition operation to be checked.

    SEMICONDUCTOR SHIFT REGISTER USING POLYCRYSTALLINE SILICON
    19.
    发明专利
    SEMICONDUCTOR SHIFT REGISTER USING POLYCRYSTALLINE SILICON 未知

    公开(公告)号：CA963169A

    公开(公告)日：1975-02-18

    申请号：CA155564

    申请日：1972-11-01

    Applicant: IBM

    Inventor： DOO VEN Y ,  HO IRVING T ,  JEN TEH-SEN

    IPC: G11C27/04 ,  G11C19/18 ,  H01L21/00 ,  H01L21/33 ,  H01L21/339 ,  H01L27/105 ,  H01L29/70 ,  H01L29/762

    Abstract: 1336301 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 17 Oct 1972 [3 Nov 1971] 47774/72 Heading H1K A capacitor structure forming part of a semiconductor device comprises a semi-conductor body, an insulating layer on a sufrace of the body, a layer of doped polycrystalline semiconductor material overlying the insulating layer, a second insulating layer on the layer of polycrystalline material and a layer of conductive material in ohmic contact with the semi-conductor body overlying the polycrystalline layer and separated therefrom by the second insulating layer, the semi-conductor body and conductive layer forming one electrode of the capacitor, the polycrystalline layer, the second electrode and the insulating layers the dielectric. As shown the device is a bucket brigade shift register wherein such capacitors are connected between the collector and base of an array of switching bipolar transistors (Figs. 1 and 2, not shown). The transistors, comprising collector 40, collector contact region 42, base 44 and emitter 46, are formed in epitaxial layer 36 on monocrystalline silicon substrate 34 after sub-collector diffusion 38 has been formed. The transistors are separated by isolation diffusions 48. Layer 36 is covered by insulating layer 50 comprising thermal SiO 2 or SiO 2 /Si 3 N 4 with apertures for emitter, base and collector contacts 16, 18, 14. Layer 52 of doped polycrystalline silicon is insulated from overlying conductive layer by thermal SiO 2 layer 54. The capacitance of the device is between extension (58) of collector terminal 14 (Fig. 3, not shown) and polycrystalline layer 52 and between. collector region 40 and layer 52, one layer being in electrical contact with base terminal 18 through opening (56) (Fig. 3, not shown) in layer 54. Preferably the base terminals extend alternatively in opposite directions to contactone of a pair of clock lines (Fig. 3, not shown), best illustrated by the prior art arrangement (Fig. 1, not shown). The various metal layers may be deposited aluminium. In an alternative construction the device uses field effect transistors (Figs. 4, 5, not shown).

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