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    Two device monolithic bipolar memory array
    1.
    发明授权
    Two device monolithic bipolar memory array 失效
    两个设备单声道双极存储器阵列

    公开(公告)号：US3697962A

    公开(公告)日：1972-10-10

    申请号：US3697962D

    申请日：1970-11-27

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM F ,  HO IRVING T ,  JEN TEH-SEN ,  PRICER W DAVID

    IPC: G11C11/403 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/4094 ,  H01L23/535 ,  H01L27/07 ,  H01L27/102 ,  G11C11/40

    CPC classification number: H01L27/1023 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/4094 ,  H01L23/535 ,  H01L27/075 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: This specification discloses a stored charged storage cell for implementation in monolithic memories. The storage cells are fabricated in an array form and are connected to accessing means for reading and writing information into and out of the array. An integrated circuit diffused common sensing line is connected to either selected rows or columns for reading and writing. These sensing lines are connected to a switchable current source. The cell itself clamps the output voltage swing and thus reduces power dissipation. The storage cells each comprise a pair of semiconductor elements for storing digital information on an associated parasitic capacitor. The pair of semiconductor devices are interconnected and operated in an AC mode so as to eliminate direct current paths and thus further prevent unnecessary power dissipation.

    Abstract translation: 本说明书公开了一种用于在单片存储器中实现的存储的充电存储单元。 存储单元以阵列形式制造并连接到用于将信息读入和写入阵列的访问装置。 集成电路漫射的公共感测线路连接到所选择的行或列用于读取和写入。 这些感测线路连接到可切换的电流源。 电池本身夹紧输出电压摆幅，从而降低功耗。 存储单元各自包括一对半导体元件，用于在关联的寄生电容器上存储数字信息。 该对半导体器件以AC模式互连和操作，以消除直流电流路径，从而进一步防止不必要的功率耗散。

    Monolithic bipolar convertible static shift register
    2.
    发明授权
    Monolithic bipolar convertible static shift register 失效
    单声双极可调稳态移位寄存器

    公开(公告)号：US3665210A

    公开(公告)日：1972-05-23

    申请号：US3665210D

    申请日：1970-06-30

    Applicant: IBM

    Inventor： HO IRVING T ,  HOWELL PETER E ,  JEN TEH-SEN

    IPC: G11C19/18 ,  G11C19/28 ,  G11C11/24 ,  G11C11/34 ,  G11C19/00

    CPC classification number: G11C19/182 ,  G11C19/28

    Abstract: A storage cell suitable for implementation as a monolithic shift register in which a pair of monolithic parasitic capacitors are selectively charged solely in response to periodic non-dc signals to set the digital state of the storage cell. Semiconductor switching means connected between the first and second capacitors is responsive to periodic signals to regenerate the cell for operation in a static mode. Alternatively, a dc circuit prevents loss of cell information during a static mode. The semiconductor switching means is virtually eliminated from the circuit by proper biasing so as to also render the cell operable for use in a dynamic shift register mode.

    High-density dynamic shift register
    3.
    发明授权
    High-density dynamic shift register 失效
    高密度动态移位寄存器

    公开(公告)号：US3621279A

    公开(公告)日：1971-11-16

    申请号：US3621279D

    申请日：1970-01-28

    Applicant: IBM

    Inventor： JEN TEH-SEN ,  PRICER WILBUR D ,  VOGL NORBERT G JR

    IPC: G11C19/18 ,  H01L27/088 ,  G11C19/00

    CPC classification number: G11C19/186 ,  H01L27/088

    Abstract: A dynamic shift register is disclosed for providing large capacity storage of digital data information in a small-volume solid-state package. A unique high-density approach is taken, involving a cell comprising n subcells capable of storing n-1 bits of data. The cells are fabricated preferably of field effect transistors embedded in a semiconductor wafer or monolith.

    Complementary field effect transistor having p doped silicon gates and process for making the same
    4.
    发明授权
    Complementary field effect transistor having p doped silicon gates and process for making the same 失效
    具有P型硅栅的补充场效应晶体管及其制造方法

    公开(公告)号：US3865654A

    公开(公告)日：1975-02-11

    申请号：US44107374

    申请日：1974-02-11

    Applicant: IBM

    Inventor： CHANG CHI SHIH ,  JEN TEH-SEN

    IPC: H01L21/8238 ,  H01L29/00 ,  H01L7/44

    CPC classification number: H01L21/823842 ,  H01L21/8238 ,  H01L29/00 ,  Y10S148/07 ,  Y10S148/122

    Abstract: An insulated gate complementary field effect transistor integrated circuit uses silicon as the gate electrode. The gates of both N- and P- channel transistors are doped with P type impurities, thereby balancing the voltage threshold characteristics of the transistors. After the P type diffusions are completed, a dip etch is used in the process to open the windows for the N type diffusions, thereby avoiding the necessity for applying photo-resist as a mask.

    Abstract translation: 绝缘栅互补场效应晶体管集成电路使用硅作为栅电极。 N沟道晶体管和P-沟道晶体管的栅极掺杂有P型杂质，从而平衡晶体管的电压阈值特性。

    SEMICONDUCTOR SHIFT REGISTER USING POLYCRYSTALLINE SILICON
    9.
    发明专利
    SEMICONDUCTOR SHIFT REGISTER USING POLYCRYSTALLINE SILICON 未知

    公开(公告)号：CA963169A

    公开(公告)日：1975-02-18

    申请号：CA155564

    申请日：1972-11-01

    Applicant: IBM

    Inventor： DOO VEN Y ,  HO IRVING T ,  JEN TEH-SEN

    IPC: G11C27/04 ,  G11C19/18 ,  H01L21/00 ,  H01L21/33 ,  H01L21/339 ,  H01L27/105 ,  H01L29/70 ,  H01L29/762

    Abstract: 1336301 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 17 Oct 1972 [3 Nov 1971] 47774/72 Heading H1K A capacitor structure forming part of a semiconductor device comprises a semi-conductor body, an insulating layer on a sufrace of the body, a layer of doped polycrystalline semiconductor material overlying the insulating layer, a second insulating layer on the layer of polycrystalline material and a layer of conductive material in ohmic contact with the semi-conductor body overlying the polycrystalline layer and separated therefrom by the second insulating layer, the semi-conductor body and conductive layer forming one electrode of the capacitor, the polycrystalline layer, the second electrode and the insulating layers the dielectric. As shown the device is a bucket brigade shift register wherein such capacitors are connected between the collector and base of an array of switching bipolar transistors (Figs. 1 and 2, not shown). The transistors, comprising collector 40, collector contact region 42, base 44 and emitter 46, are formed in epitaxial layer 36 on monocrystalline silicon substrate 34 after sub-collector diffusion 38 has been formed. The transistors are separated by isolation diffusions 48. Layer 36 is covered by insulating layer 50 comprising thermal SiO 2 or SiO 2 /Si 3 N 4 with apertures for emitter, base and collector contacts 16, 18, 14. Layer 52 of doped polycrystalline silicon is insulated from overlying conductive layer by thermal SiO 2 layer 54. The capacitance of the device is between extension (58) of collector terminal 14 (Fig. 3, not shown) and polycrystalline layer 52 and between. collector region 40 and layer 52, one layer being in electrical contact with base terminal 18 through opening (56) (Fig. 3, not shown) in layer 54. Preferably the base terminals extend alternatively in opposite directions to contactone of a pair of clock lines (Fig. 3, not shown), best illustrated by the prior art arrangement (Fig. 1, not shown). The various metal layers may be deposited aluminium. In an alternative construction the device uses field effect transistors (Figs. 4, 5, not shown).

    MASTER IMAGE CHIP ORGANIZATION TECHNIQUE OR METHOD
    10.
    发明专利
    MASTER IMAGE CHIP ORGANIZATION TECHNIQUE OR METHOD 未知

    公开(公告)号：CA1133146A

    公开(公告)日：1982-10-05

    申请号：CA337643

    申请日：1979-10-15

    Applicant: IBM

    Inventor： BALYOZ JOHN ,  CHANG CHI S ,  FOX BARRY C ,  GHAFGHAICHI MAJID ,  JEN TEH-SEN ,  MOONEY DONALD B ,  PALMIERI JOHN A

    IPC: H01L21/822 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H05K1/16 ,  H05K3/10

    Abstract: MASTER IMAGE CHIP ORGANIZATION TECHNIQUE OR METHOD Semiconductor chips are optimally structured to facilitate the maximum number of devices and circuits, and to facilitate fabrication of a wide variety of large scale integrated part numbers. Essentially, none of the semiconductor surface is dedicated for signal and power wiring channels. A master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface. This master image wiring structure makes it possible to personalize the power and signal wiring for a multiple power surface structure. The combined master image structure provides a means for optimally allocating semiconductor area for devices, functional units (micro and macro) and signal and power wiring to facilitate improved density and performance. FI9-78-014

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