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    PLURAL PROCESSOR SYSTEMS HAVING SHARED RESOURCES
    11.
    发明专利
    PLURAL PROCESSOR SYSTEMS HAVING SHARED RESOURCES 未知

    公开(公告)号：GB2171823A

    公开(公告)日：1986-09-03

    申请号：GB8525990

    申请日：1985-10-22

    Applicant: IBM

    Inventor： IRWIN JOHN WILLIAM

    IPC: G06F13/24 ,  G06F13/26 ,  G06F13/28 ,  G06K9/00 ,  G06F13/38 ,  G06F15/16 ,  G06F15/177 ,  G06F9/46

    Abstract: Data processing system including a main processor (11) and a co-processor (22) sharing the same I/O facilities (17,18,19) as the main processor (11) and running software unknown to the main processor (11). The main processor (11) can concurrently run other software and maintains priority over shared I/O facilities (17,18,19) by providing trapping logic incorporated in a random access memory and dynamically loadable by the main processor (11) which contains data related to the current useability by the co-processor (22) of a shared I/O device (17). Additional logic is associated with the co-processor (22) to manage interrupts between the co-processor (22) and the system bus (16).

    12.
    发明专利
    未知

    公开(公告)号：NO801055L

    公开(公告)日：1980-10-31

    申请号：NO801055

    申请日：1980-04-11

    Applicant: IBM

    Inventor： IRWIN JOHN WILLIAM

    IPC: B41J29/38 ,  B41J13/00 ,  B41J19/20 ,  G03G17/00 ,  G06F17/00 ,  G06K15/00 ,  G06K15/06 ,  G06K15/10 ,  H04N1/04 ,  G01D

    Abstract: In a printing device including a paper feed drum 10 and a printing array 250, the movements of the drum and array are controlled by servo systems 62 and 264. Both servo loops include a common micro-processor. During a non-printing cycle of the machine, the processor selects certain operating parameters and stores these parameters as critical operating parameters for use in subsequent printing cycles.

    15.
    发明专利
    未知

    公开(公告)号：DE2239163A1

    公开(公告)日：1973-02-22

    申请号：DE2239163

    申请日：1972-08-09

    Applicant: IBM

    Inventor： EDSTROM GENE HAROLD ,  ELWELL RUSSELL MERRITT ,  IRWIN JOHN WILLIAM

    IPC: G06F11/00 ,  G06F11/14 ,  G06F13/00 ,  G06F13/38 ,  G06F15/16 ,  G06F3/04

    Abstract: Data processing peripheral subsystems are connectable to two different types of data processing systems, each having different capabilities. For example, one data processing system Type 1 has certain error recovery procedures which are greater and more effective than those available for Type 2. The peripheral subsystem detects the type of data processing system to which it is attached and adjusts its operational procedures for emulating the operation of a Type 2 data processing system to the operational capabilities of the Type 1 data processing system without internal changes within the data processing system. The peripheral subsystem is further adapted to operate in a degraded mode with a data processing system of either type when the situation demands it.

    16.
    发明专利
    未知

    公开(公告)号：DE3852695D1

    公开(公告)日：1995-02-16

    申请号：DE3852695

    申请日：1988-10-03

    Applicant: IBM

    Inventor： FOGG RICHARD GREGORY ,  IRWIN JOHN WILLIAM

    IPC: G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G09G5/36 ,  G09G5/39 ,  G09G5/399 ,  G06F15/16 ,  G09G1/16

    Abstract: A multi-processor system includes at lteast a main processor, a co-processor and a video buffer store coupled to accept data from either of the processors for display. In order to maintain a record of data for display from the co-processor when the main processor is controlling the video buffer, a shadow video buffer is provided. This maintains an updated version of display data from the co-processor at all times. When the main processor is controlling the video buffer, the co-processor accesses the shadow buffer. When the co-processor is controlling the video buffer, it updates both the video buffer and the shadow buffer simultaneously.

    18.
    发明专利
    未知

    公开(公告)号：BR8600665A

    公开(公告)日：1986-10-29

    申请号：BR8600665

    申请日：1986-02-17

    Applicant: IBM

    Inventor： IRWIN JOHN WILLIAM

    IPC: G06K9/00 ,  G06F13/24 ,  G06F13/26 ,  G06F13/28 ,  G06F13/38 ,  G06F15/16 ,  G06F15/177

    Abstract: Data processing system including a main processor (11) and a co-processor (22) sharing the same I/O facilities (17,18,19) as the main processor (11) and running software unknown to the main processor (11). The main processor (11) can concurrently run other software and maintains priority over shared I/O facilities (17,18,19) by providing trapping logic incorporated in a random access memory and dynamically loadable by the main processor (11) which contains data related to the current useability by the co-processor (22) of a shared I/O device (17). Additional logic is associated with the co-processor (22) to manage interrupts between the co-processor (22) and the system bus (16).

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