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    IMPROVEMENTS IN ELECTRONIC CIRCUIT MODULES
    1.
    发明专利
    IMPROVEMENTS IN ELECTRONIC CIRCUIT MODULES 未知

    公开(公告)号：GB1283173A

    公开(公告)日：1972-07-26

    申请号：GB1361771

    申请日：1971-05-07

    Applicant: IBM

    Inventor： DEVORE ERNEST WILLIAM ,  HOTALING KENNETH LEGRAND

    IPC: H05K1/14 ,  H05K7/02

    Abstract: 1283173 Two part couplings INTERNATIONAL BUSINESS MACHINES CORP 7 May 1971 [29 June 1970] 13617/71 Heading H2E [Also in Division H1] Electronic circuit modules A, B, C, D (Fig. 4) have opposite surfaces'carrying plug and socket contacts respectively in order that they may be assembled into an interconnected 3 dimensional matrix. Each module (Fig. 2) comprises a -double sided printed circuit on a board 13 and a square frame 10 the frame having a central aperture to accommodate a component 12 connected to the board 13 by contacts 44. Module contact plugs-20, 24 pass through apertures in the frame wall and engage contact pads 21, 25 respectively, being soldered therein. Socket portions 23, 27 arranged on opposite faces are soldered to pads e.g. 22, are retained in groove 45 in the faces, apertures 55 (Fig. 4) communicating with the grooves to accept a plug of an adjacent unit. A third plug and socket arrangement 33 is provided in the portions 35- 38 of the frame, the socket 41 being crimped to the pin 40 said pin being soldered to pads 42. Dimples on the upper surfaces of the legs 35-38 provide a clearance for the base of the adjacent module (i.e. its circuit board) above said legs. Modules may be supported on a rack 80 (Fig. 5) by bars 100 which pass through the horizontal channels formed by a row of modules. The vertical channels also formed allow ventilation for cooling. External connections may be by tape cable e.g. 14 have suitable end connectors e.g. 83 and adaptor plugs e.g. 82. A circuit for use of the modules as a peripheral device control unit is disclosed.

    2.
    发明专利
    未知

    公开(公告)号：DE2341952A1

    公开(公告)日：1974-03-07

    申请号：DE2341952

    申请日：1973-08-20

    Applicant: IBM

    Inventor： DEVORE ERNEST WILLIAM ,  HALL PHIL HARLAN

    IPC: H03M13/00 ,  G06F11/10 ,  G06K5/00 ,  G11B20/18 ,  G11B5/02

    Abstract: A digital magnetic recording system or a signal transmission system employs an error detection and correction code capable of correcting k+n error conditions (k and n are positive integers) whenever quality signals point to an error-prone condition. Such error correction code can detect and correct k errors without pointers in a given set of data signals. At the transmitter, or during a recording operation, the recording of signal transfer is monitored. In addition, signals are recovered and processed through error detection and correction circuits for pointing to said k error conditions. Such k error conditions are then compared with the error-prone condition signals. An okay signal is provided if there are no errors or if there are k error conditions wherein the error locations within a set of data signals are pointed to both by the error-prone condition signals and the error correction code. An error condition exists if there are k+n (k=1 or more) or more errors or if the comparison for k error conditions is not met.

    DATA RECORDER/READER AND METHOD OF OPERATING SAME
    3.
    发明专利
    DATA RECORDER/READER AND METHOD OF OPERATING SAME 未知

    公开(公告)号：DE3065686D1

    公开(公告)日：1983-12-29

    申请号：DE3065686

    申请日：1980-08-21

    Applicant: IBM

    Inventor： ARTER NELSON KAY ,  DEVORE ERNEST WILLIAM ,  WILLS ARTHUR BARTON ,  ZELENKA LESLIE RAY

    IPC: G11B5/55 ,  G11B5/008 ,  G11B5/012 ,  G11B5/09 ,  G11B5/265 ,  G11B5/53 ,  G11B15/087 ,  G11B15/12 ,  G11B15/60 ,  G11B20/12 ,  G11B23/00 ,  G11B27/30 ,  G11B27/32 ,  G11B5/02 ,  G11B5/52 ,  G11B5/27

    Abstract: A data recorder/reader provides forward/backward compatibility with record members of similar physical characteristics, but differing data record track densities. In a rotating head, helical tape recorder/reader, a single head 16 has a wide write gap 17 followed by a pair of aligned half width read gaps 18 and 19. During recording at high track density, the tape is stepped between recordings by drive 27 under the control of half step circuit 29 for a distance equal to half the width W2 of the write gap and to the width W1 of each read gap. During recording at low track density, the tap is stepped between recordings by drive 27 under the control of whole step circuit 28 for a distance equal to the width W2 of the write gap. Switching between circuits 28 and 29 is effected by pole 54 of switch S1. During read back at high density, two adjacent tracks are sensed simultaneously by read gaps 18 and 19. Signals are fed back to individual read back circuits 31 and 37, those from the first read gap 18 being passed through switch 43 to data circuit 33 for immediate processing. Signals from the second read gap 19 are passed to a buffer 39 and buffered until a dead time occurs when no data is being sensed. The switch 43 is then operated to direct the buffered signals to data circuit 33 for processing. Between read backs, the tap is stepped by drive 27 under the control of whole step circuit 28 for a distance equal to the width W2 of the write gap. Circuit 28 is selected through pole 54 of switch S1 and pole 49 of switch S2. During read back at low track density, a single wide track is sensed simultaneously by read gaps 18 and 19. Signals from the first read gap 18 are processed immediately. Signals from the second read gap 19 may be inhibited or buffered for later processing in data circuit 33 in the event of error correction being required. Between read backs, the tape is stepped for a distance equal to the width W2 of the write gap.

    5.
    发明专利
    未知

    公开(公告)号：DE2732515A1

    公开(公告)日：1978-02-16

    申请号：DE2732515

    申请日：1977-07-19

    Applicant: IBM

    Inventor： DEVORE ERNEST WILLIAM ,  MCDOWELL JUDSON ALLEN

    IPC: G11B15/087 ,  G11B20/12 ,  G11B27/10 ,  G11B27/30 ,  G11B5/02

    Abstract: Each data record portion on a record member includes preamble signals for synchronizing recording apparatus with respect to data signals recorded in juxtaposition to the preamble signals. A plurality of beginning of data indicators are interleaved in the synchronizing signals for providing a plurality of independent but coacting beginning of data location pointers. Enhanced apparatus includes means responsive to any one of the location pointers to ensure a reliable start of data indication.

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