公开(公告)号：JPH08249491A

公开(公告)日：1996-09-27

申请号：JP2502395

申请日：1995-02-14

Applicant: IBM

Inventor： KAWASE KATSURA ,  NAKAMURA HIDEFUMI ,  TAKATSU YOSHIHISA

IPC: G06T11/00 ,  G06T15/40 ,  G06T15/00

Abstract: PURPOSE: To cope with such a case as to plot many spheres and pipings at a high speed. CONSTITUTION: This device is provided with a texture memory 27 for storing the color information on the surface of an object and the depth information on the object, a read means for reading the chrominance information on the surface of the object and the depth information required for plotting the object in response to the reception of a command for plotting the object stored in the memory corresponding to specified size and position, and the chrominance information and the depth information when it is required. the processing means of magnification and reduction, etc., for performing magnification, reduction and depth change processing to the chrominance information on the surface of the object and the depth information on the object, a color processing for executing a processing for the chrominance information of the surface of the object for which the processing of the magnification and the reduction, etc., is performed and a hidden surface processing means for performing a hidden surface elimination processing for the surface of the object to be plotted from the chrominance information on the surface of the object, the depth information on the abject and the position specified by the command.

公开(公告)号：JPH0877385A

公开(公告)日：1996-03-22

申请号：JP20357894

申请日：1994-08-29

Applicant: IBM

Inventor： NAKAMURA HIDEFUMI ,  MORIYAMA TAKAO ,  KAWASE KATSURA

IPC: G06T9/00 ,  G06T11/20 ,  G06T15/00 ,  G06T17/10

Abstract: PURPOSE: To efficiently execute the function of texture mapping in a computer graphics interface. CONSTITUTION: In this computer graphics device 10, a texture generator 14 is connected to fragment generators 32 to 38 through a command bus 16. The generator 14 is connected to a texture data bus 20 through a texture memory cluster 22 constituted of an address generator 62 connected to a texture coordinate bus 18, a filter 66 and eight memories 64A to 64H. In addition the generator 14 is connected to the texture data bus through clusters 24 to 28. Plotting processors 42 to 48 to which frame memories 52 to 58 are connected correspondingly are connected to the bus 20. Texture mapping is executed by efficiently utilizing the texture memory cluster.

公开(公告)号：JPH07219914A

公开(公告)日：1995-08-18

申请号：JP404094

申请日：1994-01-19

Applicant: IBM

Inventor： KAWASE KATSURA ,  MORIYAMA TAKAO

IPC: G06F15/16 ,  G06F12/08 ,  G06F15/163

Abstract: PURPOSE: To allocable data sets to the element processors of a multi-processor system at a certain time of a data string, having regularity at high speed and to efficiently perform parallel execution of them. CONSTITUTION: A reference bit is provided for a cache block, and a mechanism is added for preventing allocation with all-read from the other caches to the cache block which has not yet been referred to. When new data are read into the cache block, the reference bit becomes '0' and when that cache block is referred to from a CPU, it becomes '1'. The basic operation is identical to the all-read protocol, and when it is not necessary to perform write-back to the relevant block but it can be replaced and the reference bit is '1' concerning the data read of the other caches, these data are fetched into the cache.

公开(公告)号：JPH0554004A

公开(公告)日：1993-03-05

申请号：JP23374991

申请日：1991-08-22

Applicant: IBM

Inventor： KAWASE KATSURA ,  MATSUMOTO TAKASHI ,  MORIYAMA TAKAO

IPC: G06F13/18 ,  G06F15/16 ,  G06F15/177 ,  G06T1/20

Abstract: PURPOSE: To enable a parallel execution of instructions to snapshot of data set at an arbitrary time which are sequentially updated by string data having sequentiality, by assigning the snapshot at a high speed to an element processor of a multi-processor 22. CONSTITUTION: In each element processor 22, plural selectively lackable memories, for example, triple memories 28, are provided to obtain a high speed snapshot of a data set at an arbitrary time. The snapshot is achieved by always keeping the latest content in a master memory 30, one of the triple memories 28, and locking one of the remaining two slave memories 31 and 32 at an arbitrary time. Next, when the snapshot become necessary, the slave memory 32 which is currently unlocked is used by locking it and the slave memory 31 locked up to now is released from locking and is renewed with the same content as that in the master memory 30.