公开(公告)号：CA2011503C

公开(公告)日：1994-03-15

申请号：CA2011503

申请日：1990-03-05

Applicant: IBM

Inventor： FUKUDA MUNEHIRO ,  MATSUMOTO TAKASHI ,  NAKADA TAKEO

IPC: G06F15/173 ,  G06F9/45 ,  G06F9/52 ,  G06F15/167 ,  G06F1/12

Abstract: A number of synchronization controllers are provided for a multiprocessor system, one controller being provided for each processor and all being commonly connected to a synchronization signal bus. Each of these synchronization controllers has a synchronization wait signal transmitting means for receiving a synchronization request signal from a corresponding processor and transmitting a synchronization wait signal to the synchronization signal bus. Each controller also includes: (a) a synchronization register for specifying the other processors to be synchronized with the corresponding processor; (b) a comparator means for comparing the signal from the synchronization signal bus with the content of the synchronization register; and (c) a means for transmitting to the corresponding processor a synchronization-acknowledge signal based on the result of the comparison by the comparator means.

公开(公告)号：DE69030523T2

公开(公告)日：1997-10-23

申请号：DE69030523

申请日：1990-02-23

Applicant: IBM

Inventor： FUKUDA MUNEHIRO ,  MATSUMOTO TAKASHI ,  NAKADA TAKEO

IPC: G06F15/173 ,  G06F9/45 ,  G06F9/52 ,  G06F15/167 ,  G06F15/16 ,  G06F9/46

Abstract: A multiprocessor system wherein a plurality of processors are connected through a shared data bus, each of the processors generating synchronisation request signals in response to its instruction stream, synchronisation required among processes assigned to the processors being achieved by the synchronisation request signals, wherein indicators signifying the requirement to synchronise are embedded in the processes and there is provided a synchronisation controller to each of the processors; and a synchronisation signal bus to which the synchronisation controllers are commonly connected; and each synchronisation controllers has means for recording which processors are involved in the current process synchronisation, means for broadcasting on the synchronisation bus the current processor status in an individual portion of the communication channel provided thereby, means for snooping the synchronisation bus to monitor the total communication channel and means responsive to such snooping and to the involvement recording means to signal the associated processor that all processors recorded to be involved are indicating the same status. The system can be rendered hierarchical by clustering and can handle pipelined operations.

公开(公告)号：DE68926843D1

公开(公告)日：1996-08-22

申请号：DE68926843

申请日：1989-10-31

Applicant: IBM

Inventor： MATSUMOTO TAKASHI

IPC: G06T11/00 ,  G06T15/30 ,  G06T15/10

公开(公告)号：DE69030523D1

公开(公告)日：1997-05-28

申请号：DE69030523

申请日：1990-02-23

Applicant: IBM

Inventor： FUKUDA MUNEHIRO ,  MATSUMOTO TAKASHI ,  NAKADA TAKEO

IPC: G06F15/173 ,  G06F9/45 ,  G06F9/52 ,  G06F15/167 ,  G06F15/16 ,  G06F9/46

Abstract: A multiprocessor system wherein a plurality of processors are connected through a shared data bus, each of the processors generating synchronisation request signals in response to its instruction stream, synchronisation required among processes assigned to the processors being achieved by the synchronisation request signals, wherein indicators signifying the requirement to synchronise are embedded in the processes and there is provided a synchronisation controller to each of the processors; and a synchronisation signal bus to which the synchronisation controllers are commonly connected; and each synchronisation controllers has means for recording which processors are involved in the current process synchronisation, means for broadcasting on the synchronisation bus the current processor status in an individual portion of the communication channel provided thereby, means for snooping the synchronisation bus to monitor the total communication channel and means responsive to such snooping and to the involvement recording means to signal the associated processor that all processors recorded to be involved are indicating the same status. The system can be rendered hierarchical by clustering and can handle pipelined operations.

公开(公告)号：CA2073540A1

公开(公告)日：1993-02-23

申请号：CA2073540

申请日：1992-07-09

Applicant: IBM

Inventor： KAWASE KEI ,  MATSUMOTO TAKASHI ,  MORIYAMA TAKAO

IPC: G06F13/18 ,  G06F15/16 ,  G06F15/177 ,  G06T1/20 ,  G06F12/02 ,  G06F3/14

Abstract: JA9-91-522 MULTIPROCESSOR SYSTEM, MEMORY MANAGING SYSTEM THEREFOR, AND GRAPHICS DISPLAY SYSTEM USING THE MULTIPROCESSOR SYSTEM To provide a snapshot at an arbitrary point of time in a data set, a set which is sequentially renewed by a series of data having a sequentiality to a plurality of element processors, and, to execute instructions for the snapshot in parallel and efficiently, a plurality of memories, for example, triple memories that can be selectively locked, are provided inside of each element processor to obtain a data set snapshot at an arbitrary time at high speed. One memory among the assumed triple memories, the master memory, is used to store the newest values, and, one of the remaining two memories, (slave memories), is locked at an arbitrary time to obtain a snapshot. The unlocked slave memory is made to have the same value as the master memory. When the next snapshot is needed, that unlocked slave memory is locked while the earlier locked slave memory is unlocked and made to have the same value as the master memory.

公开(公告)号：JPH03144847A

公开(公告)日：1991-06-20

申请号：JP27733489

申请日：1989-10-26

Applicant: IBM

Inventor： MATSUMOTO TAKASHI

IPC: G06F15/16 ,  G06F9/45 ,  G06F9/52 ,  G06F15/167 ,  G06F15/177

Abstract: PURPOSE: To suppress overheads and meaningless scheduling accompanying synchronization among processors by executing a step for requesting rescheduling when it is discriminated that conditions are not valid. CONSTITUTION: The synchronization through a shared memory 4 is adopted so as to reduce the overheads and information related to the processor resources CPU1-CPUn of a system is made accessible from a user. Then, in the loop of the synchronization standby of busy wait, not only a synchronization variable is checked but also the information related to the processor resources CPU1- CPUn is checked. As the result of the checking, when the conditions for not establishing the synchronization for some time are judged, a process in the busy wait interrupts the execution of the process by itself, control is shifted to a scheduler, rescheduling is performed and the allocation of the processors to the processors CPU1-CPUn is changed. Thus, the overheads and the meaningless scheduling accompanying the synchronization among the processors CPU1- CPUn are suppressed.

公开(公告)号：JPH02238534A

公开(公告)日：1990-09-20

申请号：JP5776189

申请日：1989-03-13

Applicant: IBM JAPAN

Inventor： MATSUMOTO TAKASHI

IPC: G06F12/08 ,  G06F13/42 ,  G06F15/16

Abstract: PURPOSE:To switch the protocols without producing any overhead by executing a data operation via a private cache corresponding to a protocol accordant with the protocol type signal set on a protocol type bus. CONSTITUTION:The information is added to designate the protocols used by caches C1 - Cn when an access is given to the data on each specific storage area. The processors (memory control units) P1 - Pn output the additional information corresponding to the area including a memory to be operated as a signal at an access to the memory. The signal of the additional information is also outputted onto a common bus 1 when an access is given to the memory via the bus 1. The caches C1 - Cn connected to the bus 1 select the protocols with each relevant signal on the bus 1 and carry out the bus snoop (bus monitor). Thus the protocols of caches C1 - Cn can be switched with no overhead according to the type of the shared data.

公开(公告)号：JPH0554004A

公开(公告)日：1993-03-05

申请号：JP23374991

申请日：1991-08-22

Applicant: IBM

Inventor： KAWASE KATSURA ,  MATSUMOTO TAKASHI ,  MORIYAMA TAKAO

IPC: G06F13/18 ,  G06F15/16 ,  G06F15/177 ,  G06T1/20

Abstract: PURPOSE: To enable a parallel execution of instructions to snapshot of data set at an arbitrary time which are sequentially updated by string data having sequentiality, by assigning the snapshot at a high speed to an element processor of a multi-processor 22. CONSTITUTION: In each element processor 22, plural selectively lackable memories, for example, triple memories 28, are provided to obtain a high speed snapshot of a data set at an arbitrary time. The snapshot is achieved by always keeping the latest content in a master memory 30, one of the triple memories 28, and locking one of the remaining two slave memories 31 and 32 at an arbitrary time. Next, when the snapshot become necessary, the slave memory 32 which is currently unlocked is used by locking it and the slave memory 31 locked up to now is released from locking and is renewed with the same content as that in the master memory 30.

公开(公告)号：JPH02272684A

公开(公告)日：1990-11-07

申请号：JP9298489

申请日：1989-04-14

Applicant: IBM JAPAN

Inventor： MATSUMOTO TAKASHI

IPC: G06T15/80

Abstract: PURPOSE:To rapidly form span data by using a hyperbola generator in the case of forming span data while dividing a polygon. CONSTITUTION:The 1st to 4th straight line generating means respectively obtained by adders ADD 1 to 4, registers REG 1 to 8 and selectors SEL 1 to 4 form the coordinate value XL of scanning direction coordinate of one intersecting point, the coordinate value XR of the other scanning line direction of the intersecting point, the coordinate value ZL of a depth direction coordinate of one intersecting point, and a brightness value IL of one intersecting point. On the other hand, the 1st rectangular hyperbola generating means combining an adder ADD5, a rectangular hyperbola generator 15, a register REG9, and a selector SEL5 forms the difference dz of the depth value along a scanning line and the 2nd rectangular hyperbola generating means consisting of an adder ADD6, a rectangular hyperbola generator 16, a register REG6, and a selector SEL6 forms the difference dI of the brightness value along the scanning line. Consequently, a three-dimensional object can be rapidly plotted.

公开(公告)号：JPH02238553A

公开(公告)日：1990-09-20

申请号：JP5776289

申请日：1989-03-13

Applicant: IBM JAPAN

Inventor： FUKUDA MUNEHIRO ,  MATSUMOTO TAKASHI ,  NAKADA TAKEO

IPC: G06F15/173 ,  G06F9/45 ,  G06F9/52 ,  G06F15/167

Abstract: PURPOSE:To ensure the effective use of a multiprocessor system for plural applications by transmitting the synchronism satisfaction signals to the corresponding processors based on the result of the comparison carried out between the signal received from a synchronizing signal bus and the contents of a synchronous register. CONSTITUTION:The synchronizing signal lines SL1 - SLn of a synchronizing signal bus 2 are assigned to the processors P1 - Pn respectively. Then the syn chronizing signals Sync are transmitted from the processors P1 - Pn. A compara tor 4 samples the data on the bus 2 for each clock or each half clock and compares them with the data on a synchronous register 3. A timing control circuit 5 receives the signals Sync and returns the signals Sync and Ack accord ing to the clocks. Thus it is possible to attain at a high speed many synchronous states among the processes to which the processors P1 - Pn are assigned and to carry out plural parallel processing programs at the same time.