公开(公告)号：DE2247787A1

公开(公告)日：1974-04-18

申请号：DE2247787

申请日：1972-09-29

Applicant: IBM DEUTSCHLAND

Inventor： RUDOLPH PETER ,  LAMPE HANS HERMANN

IPC: G06F11/22 ,  G06F11/04 ,  G01R31/28

公开(公告)号：DE2245284A1

公开(公告)日：1974-04-04

申请号：DE2245284

申请日：1972-09-15

Applicant: IBM DEUTSCHLAND

Inventor： BLUM ARNOLD DIPL ING ,  IRRO FRITZ DIPL ING ,  LAMPE HANS HERMANN ,  MOHR CLAUS DIPL ING DR ,  REICHL LEOPOLD DIPL ING ,  RUDOLPH PETER

IPC: G06F11/22 ,  G06F9/30 ,  G06F9/318 ,  G06F9/40 ,  G06F9/44 ,  G06F9/448 ,  G06F9/46 ,  G06F9/18

公开(公告)号：IT1165293B

公开(公告)日：1987-04-22

申请号：IT2536579

申请日：1979-08-30

Applicant: IBM

Inventor： DRESCHER HEINZ ,  IMBUSCH HEINRICH ,  LAMPE HANS HERMANN

IPC: G01R31/3185 ,  G06F11/22 ,  G11C19/00 ,  G11C29/00 ,  G11C

公开(公告)号：DE2962897D1

公开(公告)日：1982-07-08

申请号：DE2962897

申请日：1979-07-31

Applicant: IBM

Inventor： DRESCHER HEINZ ,  IMBUSCH HINRICH ,  LAMPE HANS HERMANN

IPC: G01R31/3185 ,  G06F11/22 ,  G11C19/00 ,  G11C29/00

公开(公告)号：AU5039579A

公开(公告)日：1980-03-20

申请号：AU5039579

申请日：1979-08-29

Applicant: IBM

Inventor： BRESCHER HEINZ ,  IMBUSCH HEINRICH ,  LAMPE HANS HERMANN

IPC: G01R31/3185 ,  G06F11/22 ,  G11C19/00 ,  G11C29/00 ,  G11C19/28

公开(公告)号：DE2255643A1

公开(公告)日：1974-05-16

申请号：DE2255643

申请日：1972-11-14

Applicant: IBM DEUTSCHLAND

Inventor： RUDOLPH PETER ,  DOEHLE LOTHAR ,  POHLE WERNER ,  LAMPE HANS HERMANN

IPC: G01R13/40 ,  G06F11/32 ,  G06F3/14 ,  G06K15/20

公开(公告)号：DE2209253A1

公开(公告)日：1973-09-06

申请号：DE2209253

申请日：1972-02-26

Applicant: IBM DEUTSCHLAND

Inventor： LAMPE HANS HERMANN ,  KNAUFT GUENTHER ,  KOEDERITZ FIRTZ ,  KUNDEL GERHARD DIPL ING ,  PAINKE HELMUT DIPL ING ,  VACHENAUER ROBERT

IPC: G06F12/16 ,  G06F11/00 ,  G11C29/02 ,  G11C29/56 ,  H04L69/40

Abstract: 1365057 Testing data stores INTERNATIONAL BUSINESS MACHINES CORP 24 Jan 1973 [26 Feb 1972] 3608/73 Heading G4C The addressing circuits of an addressable data store are tested by sequentially addressing the storage locations, writing into each addressed location at least a part of its address, again sequentially addressing the storage locations, and comparing each applied address signal or part thereof with data read from that location, and generating an output AS only when the result of the comparison changes from match to mismatch or vice versa. As described, the output from the comparator is fed to a control circuit 5 which reverses the comparison criterion each time the comparator output changes to produce a signal AS which enables gate 6 thereby to record the current address at 4. The resulting recorded addresses delineate fields in the store in which the addresses do not match the stored data. Circuit 5, Fig. 2, includes two AND gates 57 and 55 enabled by a clock signal T1, the output of a latch 51 which stores the comparator output when clocked by T2 which follows T1, and the true and negated comparator outputs.

公开(公告)号：DE2165589A1

公开(公告)日：1973-07-19

申请号：DE2165589

申请日：1971-12-30

Applicant: IBM DEUTSCHLAND

Inventor： DOEHLE LOTHAR ,  LAMPE HANS HERMANN ,  POHLE WERNER ,  SKUIN PETER DIPL ING

IPC: G06F11/22 ,  G06F9/46 ,  G06F9/48 ,  G06F11/273 ,  G06F13/00 ,  G06F11/04

公开(公告)号：DE2138157A1

公开(公告)日：1973-02-22

申请号：DE2138157

申请日：1971-07-30

Applicant: IBM DEUTSCHLAND

Inventor： KOEDERITZ FRITZ ,  RUDOLPH PETER ,  LAMPE HANS HERMANN ,  SKUIN PETER DIPL ING

IPC: G06F11/07 ,  G06F11/00