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    2.
    发明专利
    未知

    公开(公告)号：DE2853546A1

    公开(公告)日：1980-06-19

    申请号：DE2853546

    申请日：1978-12-12

    Applicant: IBM DEUTSCHLAND

    Inventor： BLUM ARNOLD DIPL ING ,  GENG HELLMUTH ROLAND ING GRAD ,  SCHULZE-SCHOELLING HERMANN ING ,  SPAETH BERND DIPL ING

    IPC: G01R31/28 ,  G01R31/3183 ,  G04D7/00 ,  G06F1/04 ,  H03K5/26 ,  H04M3/22 ,  H04M3/24 ,  H03K5/18

    Abstract: In a data processing or transmission system which includes at least two synchronized clocks, for example-T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.

    4.
    发明专利
    未知

    公开(公告)号：DE3480962D1

    公开(公告)日：1990-02-08

    申请号：DE3480962

    申请日：1984-10-31

    Applicant: IBM DEUTSCHLAND

    Inventor： BLUM ARNOLD DIPL ING

    IPC: G06F13/362 ,  G06F13/364 ,  G06F15/16 ,  G06F15/177 ,  G06F13/36

    Abstract: In a bus-oriented computer system, the decision as to which unit is to receive the bus takes account of the current status of the bus system and the respective operation to be performed on the bus. For that purpose, status information of the connected units, the bus command to be executed and the address of the requested unit are fed to the allocation logic (arbiter) on separate or commonly used lines, thus avoiding idle times during the use of the bus. By evaluating the bus command, the allocation priority can be dynamically changes in order to suppress bus accesses that are bound to fail from the start.

    5.
    发明专利
    未知

    公开(公告)号：DE2853523A1

    公开(公告)日：1980-06-19

    申请号：DE2853523

    申请日：1978-12-12

    Applicant: IBM DEUTSCHLAND

    Inventor： BLUM ARNOLD DIPL ING

    IPC: G06F1/04 ,  G06F1/10

    Abstract: In a microprogrammed processor consisting of several circuitized chips, which are to be synchronously operated, each chip is provided with its own local clock generator or T-ring for deriving therefrom timing signals required during the subphases of micro instruction execution. A master clock connected to all of the T-rings by lines of equal length forces the individual T-rings to operate synchronously and keeps them operating in such a manner. In addition, reset circuitry is provided for forcing all of the T-rings to their first timing interval for initial synchronization thereof or, at an appropriate time, when a micro instruction requiring less than the maximum number of available T-ring timing signals is executed. The timing signals which are locally produced are subject to little delay on their way to the various local switching points. Thus, the entire system can be operated at a higher oscillator or master clock frequency to take advantage of the enhanced processing and transfer speeds of modern, highly integrated circuit chips.

    6.
    发明专利
    未知

    公开(公告)号：DE2555963A1

    公开(公告)日：1977-06-16

    申请号：DE2555963

    申请日：1975-12-12

    Applicant: IBM DEUTSCHLAND

    Inventor： BLUM ARNOLD DIPL ING ,  IRRO FRITZ DIPL ING ,  HEYDEN HORST VON DER ,  RICHTER STEPHAN ,  SCHULZE-SCHOELLING HERMANN ,  SCHAAL HELMUT

    IPC: G06F12/00 ,  G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/318 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F12/06 ,  G06F15/16 ,  G06F15/177 ,  G06F9/18

    Abstract: 1533770 Data processing INTERNATIONAL BUSINESS MACHINES CORP 26 Oct 1976 [12 Dec 1975] 44531/76 Heading G4A In a multiprogrammed system in which time slices are allocated to programs by chained index words, the functions of specified types of instructions in specified programs are varied if certain external and/or internal non-program conditions are satisfied. The index words are held in a store 34, each word comprising a pointer which identifies which of a number of microprograms in a control store 20 is allocated the current time slice and a link address which points to a location in a store 36 holding the address of the next index word in store 34. The number of time slices allocated to any given micro-program by the index words in store 34 may be varied. The pointer from the current word accesses a micro-program pointer from a store 38 and the micro-program pointer in turn accesses the address of the next instruction for the relevant micro-program from a store 32. The current micro-program pointer from store 38 is compared with a set of micro-program identifiers and the OP code of the next microinstruction read from the control store 20 is compared with a set of micro-instruction identifiers. If equality is detected from both comparisons and if predetermined processor internal and/or peripheral external status signals are present a function change control signal on line 11 is produced and modification information pointed to by micro-program (or possibly microinstruction) pointer register 25 is read out from a buffer 29. The decoded modification information may be used, for example, to modify the result from the ALU 51 by +1. The processor also includes a data local store 46 for A and B operands and ALU results. The store 46 may also be used for loading micro-program and micro-instruction identifiers into the comparison registers and modification information into buffer 29 under micro-instruction control. The modification arrangements allow for (micro)programming flexibility without increasing the size of the (micro-)instruction set.

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