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    1.
    发明专利
    未知

    公开(公告)号：DE2754890A1

    公开(公告)日：1979-06-13

    申请号：DE2754890

    申请日：1977-12-09

    Applicant: IBM DEUTSCHLAND

    Inventor： BEISMANN WALTER F ,  LAMPE HANS HERMANN ,  POHLE WERNER HERBERT

    IPC: G06F9/48 ,  G06F9/18

    Abstract: In a microprogram controlled processor a master mask signal, generated selectively under microprogram control, synchronizes the handling of asynchronously generated interruption requests to desired sequence stages in the interpretation of program instructions. A programmed interrupt request (PIRR) associated with the interruption priority level of the program currently in control of the processor is maintained effective for a limited period of time after the associated program assumes control. This period is determined by the presence of a PIRR (-bit) which is interruptable by any higher priority level interrupt request. If a PIRR bit representing an interrupted program is still on when servicing of a higher priority level interrupt request is concluding control is returned to the interrupted program. In order to avoid possibly locking out programs which are not associated with asynchronously generated interrupt requests-e.g., supervisor programs-a pre-settable interval timer is provided for operating after a predetermined time interval to force the setting of a PIRR bit and thereby force control to be transferred eventually to such programs.

    DATA PROCESSING SYSTEM
    3.
    发明专利
    DATA PROCESSING SYSTEM 未知

    公开(公告)号：GB1243619A

    公开(公告)日：1971-08-25

    申请号：GB2336770

    申请日：1970-05-14

    Applicant: IBM

    Inventor： HEYDEN HORST VON DER ,  HARTWICH REINHARD ,  LAMPE HANS HERMANN ,  REICHL LEOPOLD

    IPC: G06F11/00 ,  G06F13/00 ,  G06F13/42

    Abstract: 1,243,619. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 14 May, 1970 [27 June, 1969], No. 23367/70. Heading G4A. A data processing system comprises a CPU connected (e.g. by a ring bus) to a plurality of ancillary units (e.g. I/O control units or other CPU's), each of which includes means to generate a unit selected signal when it correctly or falsely responds to an address signal received from the CPU, there being means to generate a warning signal if two or more of the ancillary units generate unit selected signals in response to the same address signal. A unit selected signal is generated if an address bus portion of the ring bus has the address of the unit on it and at least one bit on a data bus portion of the ring bus is 1. The unit selected signal is ORed on to a line of the ring bus, and if the incoming portion of this line at any unit producing a unit selected signal already has such a signal on it, a warning signal is ORed on to another line of the ring bus. The CPU responds to the warning signal causing each unit producing a unit selected signal to identify itself to the CPU by a signal on a respective line.

    IMPROVEMENTS IN AND RELATING TO DATA PROCESSING SYSTEMS
    4.
    发明专利
    IMPROVEMENTS IN AND RELATING TO DATA PROCESSING SYSTEMS 未知

    公开(公告)号：GB1243160A

    公开(公告)日：1971-08-18

    申请号：GB2225670

    申请日：1970-05-08

    Applicant: IBM

    Inventor： KNAUFT GUNTER ,  KOEDERITZ FRITZ ,  LAMPE HANS HERMANN ,  PAINKE HELMUT ,  REICHL LEOPOLD ,  VACHENAUER ROBERT ,  VOGT EDWIN ,  WEBER HERMANN

    IPC: G06F11/22 ,  G06F11/267 ,  G06F11/273 ,  G06F13/00 ,  G06F13/42

    Abstract: 1,243,160. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 8 May, 1970 [30 May, 1969], No. 22256/70. Heading G4A. A data processing system includes a CPU, ancillary (e.g. I/O) units connected thereto by a ring bus system comprising an address bus and a data bus, and switching means selectively operable in response to a signal indicative of the absence of execution of a programme instruction involving communication between the CPU and the ancillary units, to apply an address of an ancillary unit defined by manually settable test means to the address bus, the addressed unit supplying data via the data bus to the CPU. The switching means only operates in response to the signal in this way if a manual mode switch is set to "I/O display", the data sent to the CPU being sense data which is displayed on lamps on the CPU control panel. If the mode switch is set to "I/O status stop", then in the presence of the "signal" mentioned above, the machine stops (i.e. at the address defined by the manually settable test means) when the contents of the data bus equal the setting of further manual switches. When test and maintenance work as above is not being performed, the manually settable test means and the further manual switches are used as conventional address and data configuration switches, and the lamps are used for displaying register and storage contents.

    6.
    发明专利
    未知

    公开(公告)号：DE2355994A1

    公开(公告)日：1975-07-03

    申请号：DE2355994

    申请日：1973-11-09

    Applicant: IBM DEUTSCHLAND

    Inventor： LAMPE HANS HERMANN ,  RUDOLPH PETER ,  HAHN GUENTER

    IPC: G01R13/00 ,  G01R13/40 ,  G01R13/04

    Abstract: An arrangement for the dynamic direct display of pulses in the nanosecond range operates without oscilloscopes or other special display apparatus. To display pulse timing or amplitude characteristics, a pulse sequence is applied to an equidistant tapped delay line, the output from each tap being connected to a bistable storage element with an indicator lamp in the output. A plurality of indicator lamps are arranged in the form of a matrix. If a pulse occurs on a tap during a sampling interval, the associated indicator lamp is turned on. The sequence and identity of the turned on indicators is indicative of the pulse spacing and the pulse width in the pulse sequence.

    10.
    发明专利
    未知

    公开(公告)号：DE2337159A1

    公开(公告)日：1975-02-13

    申请号：DE2337159

    申请日：1973-07-21

    Applicant: IBM DEUTSCHLAND

    Inventor： DRESCHER HEINZ ,  RUDOLPH PETER ,  LAMPE HANS HERMANN ,  POHLE WERNER ,  DOEHLE LOTHAR

    IPC: G06F9/48 ,  G06F13/18 ,  G06F13/366 ,  G06F9/18

    Abstract: A priority control circuit for establishing connections between a data handling system element and a number of subsystems wherein request signals from subsystems are scanned and granted service in a sequence which is determined by their position in a priority ranking order. The scanner returns to the beginning of the order immediately after a request has been granted, the subsystem just serviced being bypassed in the next scan until all of the remaining request signals have been processed. Each time a request signal is encountered and service granted, the scanner returns to the beginning of the order, a new scan is begun and all prior requests serviced are bypassed. In the absence of any other requests or after all of the request signals have been serviced the bypassed subsystems are unlocked and a scan of all requests is begun.

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