公开(公告)号：MY111733A

公开(公告)日：2000-12-30

申请号：MYPI19890548

申请日：1989-04-26

Applicant: IBM

Inventor： PATRICK MAURICE BLAND ,  MARK EDWARD DEAN ,  PHILIP ERNA MILLING

IPC: G06F13/36 ,  G06F9/44 ,  G06F9/445 ,  G06F13/362

Abstract: A MULTI-BUS MICROCOMPUTER SYSTEM INCLUDES A CACHE SUBSYSTEM AND AN ARBITRATION SUPERVISOR. A CPU IS PROVIDED WITH A PREEMPT SIGNAL SOURCE WHICH GENERATES A PREEMPT SIGNAL IN CPU CYCLES EXTENDING BEYOND A SPECIFIED DURATION. THE PREEMPT SIGNAL IS EFFECTIVE AT ANY DEVICE HAVING ACCESS TO THE BUS TO INITIATE AN ORDERLY TERMINATION OF THE BUS USAGE. WHEN THAT DEVICE SIGNALS ITS TERMINATION OF BUS USAGE, THE ARBITRATION SUPERVISOR CHANGES THE STATE OF AN ARB/GRANT CONDUCTOR, WHICH HAD BEED IN THE GRANT PHASE, TO THE ARBITRATION PHASE. DURING THE ARBITRATION PHASE EACH OF THE DEVICES (OTHER THAN THE CPU) COOPERATES IN AN ARBITRATION MECHANISM FOR BUS USAGE DURING THE NEXT GRANT PHASE. ON THE OTHER HAND, THE CPU, HAVING ASSERTED PREEMPT, RESPONDS TO A SIGNAL INDICATING INITIATION OF THE ARBITRATION PHASE BY IMMEDIATELY ACCESSING THE SYSTEM BUS.(FIG. 2)

公开(公告)号：MY104738A

公开(公告)日：1994-05-31

申请号：MYPI19890547

申请日：1989-04-26

Applicant: IBM

Inventor： RALPH MURRAY BEGUN ,  PATRICK MAURICE BLAND ,  MARK EDWARD DEAN

IPC: G06F9/38 ,  G06F12/08

Abstract: ANY INCOMPATIBILITY BETWEEN PIPELINED OPERATIONS (SUCH AS IS AVAILABLE IN THE 80386) AND DYNAMIC BUS SIZING (ALLOWING THE PROCESSOR TO OPERATE WITH DEVICES OF 8-, 16- AND 32-BIT SIZES IS ACCOMMODATED BY USE OF AN ADDRESSES DECODER AND ENSURING THAT DEVICE ADDRESSES FOR CACHEABLE DEVICES ARE IN A FIRST PREDETERMINED RANGE AND ANY DEVICE ADDRESSES FOR NON-CACHEABLE DEVICES ARE NOT IN THAT PREDETERMINED RANGE. SINCE BY DEFINITION CACHEABLE DEVICES ARE 32-BIT DEVICES, PIPELINED OPERATION IS ALLOWED ONLY IF THE ADDRESS DECODER INDICATES THE ACCESS IS TO A CACHEABLE DEVICE.. IN THAT EVENT, A NEXT ADDRESS SIGNAL IS PROVIDED TO THE 80386. THIS ALLOWS THE 80386 TO PROCEED TO A FOLLOWING CYCLE PRIOR TO COMPLETION OF THE PREVIOUS CYCLE. FOR ACCESES WHICH ARE TO DEVICES WHOSE ADDRESS INDICATE THEY ARE NON-CACHEABLE, A NEXT ADDRESS SIGNAL IS WITHHELD UNTIL THE CYCLE IS COMPLETED, I.E. WITHOUT PIPELINING. THE INVENTION FURTHER PROVIDES FOR PROPER FOR INTERFACE BETWEEN A DMA MECHANISM (DRIVEN BY A FIRST CLOCK) AND A CPU LOCAL BUS SUBSYSTEM (DRIVEN BY AN ENTIRELY DIFFERENT CLOCK). DATA PROVIDED BY THE DMA MECHANISM IS LATCHED INTO AN INTERFACE BETWEEN THE CPU LOCAL BUS AND THE SYSTEM BUS, AND A DMA CYCLE COMPLETED. ONLY AFTER COMPLETION OF THE DMA CYCLE IS DETECTED, IS THE CYCLE ON THE CPU LOCAL BUS ALLOWED TO COMPLETE. IN THIS FASHION, THE CPU CAN GO ON TO A FOLLOWING OPERATION AND BE ASSURED THAT THE DMA MECHANISM IS NO LONGER DRIVING THE SYSTEM BUS. (FIG2)

公开(公告)号：MY104737A

公开(公告)日：1994-05-31

申请号：MYPI19890549

申请日：1989-04-26

Applicant: IBM

Inventor： PATRICK MAURICE BLAND ,  MARK EDWARD DEAN

IPC: G06F7/00 ,  G06F13/36 ,  G11C11/401 ,  G06F13/362 ,  G11C7/00 ,  G11C7/10

Abstract: A COMPUTER SYSTEM IS PROVIDED IN WHICH MEMORY ACCESS TIME IS SUBSTANTIALLY REDUCED. AFTER ROW ADDRESS STROBE (RAS) AND COLUMN ADDRESS STROBE (CAS) SIGNALS ARE USED TO SELECT A PARTICULAR ADDRESS IN A MEMORY DURING A FIRST MEMORY CYCLE, THE ADDRESSED DATA IS LATCHED FOR LATER TRANSFER TO A DATA BUS. A CAS PRECHARGE OF THE MEMORY IS THEN CONDUCTED AFTER SUCH LATCHING AND PRIOR TO THE END OF THE FIRST MEMORY CYCLE BEFORE THE COMMENCEMENT OF THE SECOND MEMORY CYCLE. (FIG. 4)

公开(公告)号：MY108557A

公开(公告)日：1996-10-31

申请号：MYPI19890550

申请日：1989-04-26

Applicant: IBM

Inventor： RALPH MURRAY BEGUN ,  PATRICK MAURICE BLAND ,  MARK EDWARD DEAN

IPC: G06F12/08

Abstract: A MICROCOMPUTER SYSTEM EMPLOYING AN 80386 CPU AND AN 82835 CACHE CONTROLLER HAS THE CAPABILITY OF FUNCTIONING WITH DYNAMIC BUS SIZING (WHERE THE CPU INTERACTS WITH DEVICES WHICH MAY OR MAY NOT BE 32-BITS WIDE), AS WELL AS POSTED WRITE CAPABILITY. UNFORTUNATELY, THE TWO CAPABILITIES HAVE THE POSSIBILITY OF AN INCOMPATIBILITY IF A WRITE CYCLE IS POSTED TO A DEVICE WHICH CANNOT TRANSFER 32 BITS ON A SINGLE CYCLE. THE PRESENT INVENTION PROVIDES LOGIC TO OVERCOME THIS INCOMPATIBILITY. AN ADDRESS DECODER IS PROVIDED TO DECODE THE TAG PORTION OF AN ADDRESS ASSERTED ON A CPU LOCAL BUS TO DETERMINE IF THE ASSERTED ADDRESS IS INSIDE OR OUTSIDE A RANGE OF ADDRESSES WHICH DEFINE CACHEABLE DEVICES. ANY CACHEABLE DEVICE IS BY DEFINITION 32 BITS WIDE AND THEREFORE POSTED WRITES ARE ALLOWED ONLY TO CACHEABLE DEVICES. ACCORDINGLY, THE MICROCOMPUTER EMPLOYING THE INVENTION POSTS WRITE CYCLES TO CACHEABLE DEVICES; WRITE CYCLES TO NON-CACHEABLE DEVICES ARE INHIBITED FROM BEING POSTED. (FIG.2)

公开(公告)号：MY106968A

公开(公告)日：1995-08-30

申请号：MYPI19890552

申请日：1989-04-26

Applicant: IBM

Inventor： RALPH MURRAY BEGUN ,  PATRICK MAURICE BLAND ,  MARK EDWARD DEAN

IPC: G06F12/08

Abstract: IN AN 80386/82385 MICROCOMPUTER SYSTEM, THE TIMING REQUIREMENTS PLACED ON NON-CACHE MEMORY COMPONENTS BY THE 82385 ARE MORE STRINGENT THAN THE TIMING REQUIREMENTS PLACED ON THE NON-CACHE MEMORY COMPONENTS BY THE 80386. THE PRESENT INVENTION OPERATES ON THE 82385 CACHE WRITE ENABLE (CWE) SIGNALS, AND DELAYS THOSE SIGNALS IN THE EVENT OF A READ MISS. DELAYING THE CWE SIGNALS RELAXES THE TIMING REQUIREMENTS PLACED ON NON-CACHE MEMORY COMPONENTS AND AT THE SAME TIME DOES NOT IMPACT WAIT STATE PARAMETERS FOR READ MISS OPERATIONS.(FIG. 2)

公开(公告)号：MY104736A

公开(公告)日：1994-05-31

申请号：MYPI19890551

申请日：1989-04-26

Applicant: IBM

Inventor： SUSAN LYNN TEMPEST ,  KEVIN GERARD KRAMER ,  GENE JOSEPH GAUDENZI ,  PATRICK MAURICE BLAND ,  MARK EDWARD DEAN

IPC: G06F11/10 ,  G06F13/38 ,  G06F13/40 ,  H03K3/288 ,  H03K19/082

Abstract: A CIRCUIT FOR BUFFERING AND PARITY CHECKING DIGITAL DATA COMMUNICATED BETWEEN FIRST AND SECOND DATA BUSES INCLUDES A PLURALITY OF BIDIRECTIONAL BIT BUFFER CIRCUITS. EACH OF THE BIDIRECTIONAL BIT BUFFER CIRCUITS INCLUDES: A FIRST DATA PATH COMPRISING A DATA RECEIVER, LATCH, AND DRIVER CONNECTED IN SERIES BETWEEN THE FIRST AND SECOND DATA BUSES, RESPECTIVELY: A SECOND DATA PATH COMPRISING A DATA RECEIVER, LATCH AND DRIVER CONNECTED IN SERIES BETWEEN THE SECOND AND FIRST DATA BUSES, RESPECTIVELY; CONTROL MECHANISMS FOR CONTROLLING THE DRIVERS TO SELECTIVELY PLACE THE OUTPUT OF THE DRIVERS IN AN ACTIVE DRIVING OR HIGH IMPEDANCE STATE; AND CONTROL MECHANISMS FOR CONTROLLING THE DATA LATCHES TO SELECTIVELY LATCH OR PASS THROUGH DATA. A PARITY GENERATING CIRCUIT IS CONNECTED AT THE OUTPUT OF THE LATCH IN THE FIRST DATA PATH OF EACH OF THE BIDIRECTIONAL BIT BUFFER CIRCUITS FOR GENERATING A PARITY BIT RESPONSIVE TO THE DATA AT THE OUTPUT OF THESE LATCHES. A TRANSPARENT LATCH AND DRIVER CIRCUIT WITH PHASE SPLITTER ARE PROVIDED FOR INCREASING THE SPEED OF THE CIRCUIT WITHOUT SUBTANTIALLY INCREASING THE POWER REQUIREMENTS. (FIG. 1)