公开(公告)号：MY123847A

公开(公告)日：2006-06-30

申请号：MYPI19974824

申请日：1997-10-14

Applicant: IBM

Inventor： KENNETH MICHAEL FALLON ,  HORMAZDYAR MINOCHER DALAL ,  GENE JOSEPH GAUDENZI ,  CYNTHIA SUSAN MILKOVICH

IPC: H05K3/34 ,  H01L21/56 ,  H01L21/60 ,  H01L23/498 ,  H01L23/538 ,  H05K1/18 ,  H05K3/00 ,  H05K13/04

Abstract: A STRUCTURE AND METHOD IS DISCLOSED FOR DIRECTLY ATTACHING A DEVICE (42,44,46,48) OR PACKAGE ON FLEXIBLE ORGANIC CIRCUIT CARRIERS (23) HAVING LOW COST AND HIGH RELIABILITY.IC CHIPS WITH A NEW SOLDER INTERCONNECT STRUCTURE, COMPRISED OF A LAYER (43) OF PURE TIN, DEPOSITED ON THE TOP OF HIGH MELTING PB-SN SOLDER BALLS (41) ARE EMPLOYED FOR JOINING. THESE METHODS, TECHNIQUES AND METALLURGICAL STRUCTURES ENABLES DIRECT ATTACHMENT OF ELECTRONIC DEVICES OF ANY COMPLEXITY TO ANY SUBSTRATE AND TO ANY LEVEL OF PACKAGING HIERARCHY.ALSO, DEVICES OR PACKAGES HAVING OTHER JOINING TECHNOLOGIES, EG. SMT, BGA, TBGA, ETC. COULD BE JOINED ONTO THE FLEXIBLE CIRCUIT CARRIER.(FIG.6)

公开(公告)号：MY112563A

公开(公告)日：2001-07-31

申请号：MYPI19931905

申请日：1989-04-26

Applicant: IBM

Inventor： SUSAN LYNN TEMPEST ,  KEVIN GERARD KRAMER ,  GENE JOSEPH GAUDENZI

IPC: H03K19/177 ,  G06F11/10 ,  G06F13/38 ,  G06F13/40 ,  H03K3/288 ,  H03K19/082

Abstract: A CIRCUIT FOR BUFFERING AND PARITY CHECKING DIGITAL DATA COMMUNICATED BETWEEN FIRST AND SECOND DATA BUSES (52, 54) ,INCLUDES A PLURALITY OF BIDIRECTIONAL BIT BUFFER CIRCUITS (CO-C7). EACH OF THE BIDIRECTION BIT BUFFER CIRCUITS INCLUDES: A FIRST DATA PATH COMPRISING A DATA RECEIVER (57), LATCH (58), AND DRIVER (60) CONNECTED IN SERIES BETWEEN THE FIRST AND SECOND DATA BUSES, RESPECTIVELY; A SECOND DATA PATH COMPRISING A DATA RECEIVER (62), LATCH (64) AND DRIVER (66) CONNECTED IN SERIES BETWEEN THE SECOND AND FIRST DATA BUSES, RESPECTIVELY; CONTROL MECHANISMS FOR CONTROLLING THE DRIVERS TO SELECTIVELY PLACE THE OUTPUT OF THE DRIVERS IN AN ACTIVE DRIVING OR HIGH IMPEDANCE STATE; AND CONTROL MECHANISMS FOR CONTROLLING THE DATA LATCHES TO SELECTIVELY LATCH OR PASS THROUGH DATA. A PARITY GENERATING CIRCUIT (68) IS CONNECTED AT THE OUTPUT OF THE LATCH IN THE FIRST DATA PATH OF EACH OF THE BIDIRECTIONAL BIT BUFFER CIRCUITS FOR GENERATING A PARITY BIT RESPONSIVE TO THE DATA AT THE OUTPUT OF THESE LATCHES. A TRANSPARENT LATCH AND DRIVER CIRCUIT WITH PHASE SPLITTER (100) ARE PROVIDED FOR INCREASING THE SPEED OF THE CIRCUIT WITHOUT SUBSTANTIALLY INCREASING THE POWER REQUIREMENTS.(FIG. 2)

公开(公告)号：MY104736A

公开(公告)日：1994-05-31

申请号：MYPI19890551

申请日：1989-04-26

Applicant: IBM

Inventor： SUSAN LYNN TEMPEST ,  KEVIN GERARD KRAMER ,  GENE JOSEPH GAUDENZI ,  PATRICK MAURICE BLAND ,  MARK EDWARD DEAN

IPC: G06F11/10 ,  G06F13/38 ,  G06F13/40 ,  H03K3/288 ,  H03K19/082

Abstract: A CIRCUIT FOR BUFFERING AND PARITY CHECKING DIGITAL DATA COMMUNICATED BETWEEN FIRST AND SECOND DATA BUSES INCLUDES A PLURALITY OF BIDIRECTIONAL BIT BUFFER CIRCUITS. EACH OF THE BIDIRECTIONAL BIT BUFFER CIRCUITS INCLUDES: A FIRST DATA PATH COMPRISING A DATA RECEIVER, LATCH, AND DRIVER CONNECTED IN SERIES BETWEEN THE FIRST AND SECOND DATA BUSES, RESPECTIVELY: A SECOND DATA PATH COMPRISING A DATA RECEIVER, LATCH AND DRIVER CONNECTED IN SERIES BETWEEN THE SECOND AND FIRST DATA BUSES, RESPECTIVELY; CONTROL MECHANISMS FOR CONTROLLING THE DRIVERS TO SELECTIVELY PLACE THE OUTPUT OF THE DRIVERS IN AN ACTIVE DRIVING OR HIGH IMPEDANCE STATE; AND CONTROL MECHANISMS FOR CONTROLLING THE DATA LATCHES TO SELECTIVELY LATCH OR PASS THROUGH DATA. A PARITY GENERATING CIRCUIT IS CONNECTED AT THE OUTPUT OF THE LATCH IN THE FIRST DATA PATH OF EACH OF THE BIDIRECTIONAL BIT BUFFER CIRCUITS FOR GENERATING A PARITY BIT RESPONSIVE TO THE DATA AT THE OUTPUT OF THESE LATCHES. A TRANSPARENT LATCH AND DRIVER CIRCUIT WITH PHASE SPLITTER ARE PROVIDED FOR INCREASING THE SPEED OF THE CIRCUIT WITHOUT SUBTANTIALLY INCREASING THE POWER REQUIREMENTS. (FIG. 1)

公开(公告)号：MY103880A

公开(公告)日：1993-09-30

申请号：MYPI19890513

申请日：1989-04-21

Applicant: IBM

Inventor： GENE JOSEPH GAUDENZI

IPC: H03K17/04 ,  H03K19/013 ,  H03K19/082 ,  H03K19/086

Abstract: A CIRCUIT INCLUDES A SET OF SEVEN NPN TRANSISTORS, A SCHOTTKY DIODE, AND SEVERAL RESISTORS. THE SIGNAL IS CONNECTED FROM THE INPUT SECTION TO THE OUTPUT SECTION DIRECTLY FROM THE BASE OF A TRANSISTOR IN THE INPUT CIRCUIT TO THE BASE OF THE LOWER OUTPUT TRANSISTOR, WHICH IS CONNECTED WITH ITS COLLECTOR EMITTER CONNECTION IN PARALLEL WITH THE EMITTER RESISTOR OF THE INPUT TRANSISTORS WHICH RECEIVE THE INPUT SIGNALS TO THE CIRCUIT. TWO TRANSISTORS ARE CONNECTED TO INPUT TERMINALS TO PROVIDE A POSSIBLE NOR ARRANGEMENT ALTHOUGH ONE OF THEM ALONE CAN BE USED IF THE REQUIREMENT OF THE CIRCUIT IS SIMPLY FOR AN INVERTER CIRCUIT. THE OUTPUT TRANSISTORS COMPRISE A PA CIRCUIT INCLUDES A SET OF SEVEN NPN TRANSISTORS, A SCHOTTKY DIODE, AND SEVERAL RESISTORS. THE SIGNAL IS CONNECTED FROM THE INPUT SECTION TO THE OUTPUT SECTION DIRECTLY FROM THE BASE OF A TRANSISTOR IN THE INPUT CIRCUIT TO THE BASE OF THE LOWER OUTPUT TRANSISTOR, WHICH IS CONNECTED WITH ITS COLLECTOR EMITTER CONNECTION IN PARALLEL WITH THE EMITTER RESISTOR OF THE INPUT TRANSISTORS WHICH RECEIVE THE INPUT SIGNALS TO THE CIRCUIT. TWO TRANSISTORS ARE CONNECTED TO INPUT TERMINALS TO PROVIDE A POSSIBLE NOR ARRANGEMENT ALTHOUGH ONE OF THEM ALONE CAN BE USED IF THE REQUIREMENT OF THE CIRCUIT IS SIMPLY FOR AN INVERTER CIRCUIT. THE OUTPUT TRANSISTORS COMPRUSH-PULL OUTPUT SECTION. (FIG. 1)