公开(公告)号：JP2002171247A

公开(公告)日：2002-06-14

申请号：JP2001221146

申请日：2001-07-23

Applicant: IBM

Inventor： DAVID WILLIAM BOOSURAA ,  MARK EDWARD DEAN ,  NGO HUNG CAI ,  ANDREW CHRISTIAN ZIMMERMAN

IPC: H03L7/22 ,  G06F13/00 ,  G06F15/163 ,  G06F15/177 ,  H03L7/23 ,  H04L7/00

Abstract: PROBLEM TO BE SOLVED: To provide a node synchronization method and apparatus which can be used for a different machine kind mixing computer system in which a common system clock is not shared. SOLUTION: Time stamps are added to a transaction request. These time stamps can be registers to be incremented by a system clock based on a time value. Nodes are respectively provided with exclusive system clocks, and the frequencies of those clocks can be deviated. When the deviation of the value is large, data updated by a multi-processor computer system can be lost. The relative phase of a master time register to one or more slave time registers is monitored. A frequency synthesizer whose resolution is high and whose high speed frequencies are adjustable is connected to the system clock. When anY phase shift is detected in the master and slave time values, the output of the frequency synthesizer is changed so that the phases of the two signals can be matched into an original state.

公开(公告)号：JP2000250882A

公开(公告)日：2000-09-14

申请号：JP2000045824

申请日：2000-02-23

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  MARK EDWARD DEAN ,  DAVID BRIAN GRASCO

IPC: G06F12/08 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To avoid a lie block by completing any one of two requests in response to a request from the processor of a first node so as to invalidate the remote copy of a cache line stored in a cache memory. SOLUTION: A first request is selected so as to win (namely, Retry is not received yet). When an invalidation request is transferred to a requested remote node by a node controller 19 on the side of home node, a special bit called AutoRetry bit is set in a transaction. Read (RWITM) intending a correction from the home node 11 is repeated on the side of remote node 12 and Retry is locally performed. When Dclaim request from the remote node 12 is tried again back to a processor 24a, the opportunity to efficiently complete the RWITM request from the home node 11 on a local bus in the remote node 12 is increased.

公开(公告)号：JP2000112910A

公开(公告)日：2000-04-21

申请号：JP18183999

申请日：1999-06-28

Applicant: IBM

Inventor： CARPENTER GARY D ,  MARK EDWARD DEAN ,  DAVID BRIAN GLASCO ,  RICHARD NICHOLAS ACHETTA JR

IPC: G06F15/177 ,  G06F12/08 ,  G06F13/38 ,  G06F15/17

Abstract: PROBLEM TO BE SOLVED: To provide a nonuniform memory access(NUMA) computer system having a short inter-node communication waiting duration by providing a buffer control logic or the like for extracting a specified communication transaction from a transaction buffer and processing it by a third processing node. SOLUTION: This NUMA computer system 8 is provided with the transaction buffer connected to a mutual connecting means. This transaction buffer stores a communication transaction which defines the processing node excepting for a third processing node 10c as the destination (target). Corresponding to the determination to process the specified communication transaction, which originally defines the other processing node as the destination, by the third processing node 10c, the buffer control logic connected to the transaction buffer extracts the specified communication transaction from the transaction buffer and the transaction is processed by the third processing node 10c.

公开(公告)号：JP2006221628A

公开(公告)日：2006-08-24

申请号：JP2006019727

申请日：2006-01-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BOYD KENNETH W ,  DAY KENNETH FAIRCLOUGH III ,  MARK EDWARD DEAN ,  WOLFGANG JOHN J

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/00

CPC classification number: G06F11/2097 ,  G06F11/1662 ,  G06F11/2064 ,  G06F11/2071

Abstract: PROBLEM TO BE SOLVED: To enable a computing system to recover from a failure in a short period.
SOLUTION: The computing system generates data and metadata in a computational device. The generated data is stored in a first physical storage device 102 connected to the computational device. The generated metadata is stored temporarily in the computational device. These data and metadata are replicated to a second physical storage device 104. The replicated data and the replicated metadata 118 in the second physical storage device 104 are used to recover from a failure of at least one of the computational device and the first physical storage device 102.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：使计算系统能够在短时间内从故障中恢复。

解决方案：计算系统在计算设备中生成数据和元数据。 生成的数据被存储在连接到计算设备的第一物理存储设备102中。 生成的元数据临时存储在计算设备中。 这些数据和元数据被复制到第二物理存储设备104.第二物理存储设备104中的复制数据和复制的元数据118用于从计算设备和第一物理存储设备中的至少一个的故障中恢复 （C）2006年，JPO＆NCIPI

公开(公告)号：JP2002278921A

公开(公告)日：2002-09-27

申请号：JP2002074116

申请日：2002-03-18

Applicant: IBM

Inventor： BEAMAN DANIEL PAUL ,  CARPENTER GARY D ,  MARK EDWARD DEAN ,  VOIGT WENDEL GLENN

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for arbitrating bus control between a first bus master having a two-way handshake bus acquirement protocol and a second bus master having a one-way bus acquirement protocol. SOLUTION: The method and system for arbitrating the two bus masters having the two different bus acquirement protocols are provided. The control of a bus is taken up from the first bus master in response to the output of a bus request by the second bus master when the first bus master controls the bus. When an arbitration controller transmits a signal for ordering the first bus master to terminate a bus transaction, the control of the bus is given to the second bus master. When the second bus master terminates the bus request, the control of the bus is given to the first bus master and a signal for confirming the permission of control is transmitted from the arbitration controller to the first bus master.

公开(公告)号：JP2000250884A

公开(公告)日：2000-09-14

申请号：JP2000045976

申请日：2000-02-23

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  MARK EDWARD DEAN ,  DAVID BRIAN GRASCO

IPC: G06F9/52 ,  G06F12/08 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To improve a method for evicting a cache line from a loose directory by writing data from a corrected cache line back to the local system memory of a node and evicting an entry from the loose directory later. SOLUTION: First of all, when corrected data are tried to return to the system memory, a correction intended read (RWITM) transaction can be tried again by any reason except the generation of retry by a processor. In this case, the RWITM transaction is forcedly issued again to a transaction reception unit by an AutoRetry mode. Secondly, it is possible for a corrected cache line to be absent in the remote node 10b and RWITM receives an erasure response. Afterwards, the transaction reception unit of a node controller 20b returns a response to an eviction logic and completes the eviction.

公开(公告)号：JP2000181886A

公开(公告)日：2000-06-30

申请号：JP34017199

申请日：1999-11-30

Applicant: IBM

Inventor： GARY DALE CARPENTER ,  PHILIPPE LOUIS DEBACKER ,  MARK EDWARD DEAN ,  DAVID BRIAN GRASCO ,  RONALD RIN ROCKHOLD

IPC: G06F15/173 ,  G06F9/48 ,  G06F15/177 ,  G06F9/46

Abstract: PROBLEM TO BE SOLVED: To obtain an interruption processing mechanism equipped with an efficient mechanism for the path specification and transmission of interruption by incorporating a processor which receives external interruption and an interruption source which generate the external interruption. SOLUTION: An NUMA computer system 6 includes plural process nodes 8a to 8n which are interconnected through node interconnection 22. Each memory controller 17 includes an interruption destination unit(IDU) 19. The IDU 19 includes plural registers and logic units which facilitate the path specification and process of interruption. An input/output device 32 and a storage device 34 generate interruptions for a notice of the reception of an input value and a report on error conditions through an interruption request line 35. These external interruptions are collected by interruption source units(ISU) 28a and 28b. The ISU 28 allocates the path of an external interruption to the IDU 19, which passes the external interruption and other interruptions to a local processor 10 through an interruption request line 36 for processing.

公开(公告)号：JP2002100985A

公开(公告)日：2002-04-05

申请号：JP2001221160

申请日：2001-07-23

Applicant: IBM

Inventor： DAVID WILLIAM BOOSURAA ,  MARK EDWARD DEAN ,  NGO HUNG CAI ,  ANDREW CHRISTIAN ZIMMERMAN

IPC: H03L7/22 ,  H03L7/08 ,  H03L7/23 ,  H04L7/033

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for adjusting the generated frequency, especially a frequency synthesizer capable of performing the frequency adjustment of high resolution at high speed, using a multi-stage frequency synthesizer. SOLUTION: The initial stage of the frequency synthesizer is a conventional phase-locked loop connected to a dynamically variable frequency divider. There are one or more intermediate stages provided with the forward part of the phase-locked loop connected to the dynamically variable frequency divider for performing feedback through a fixed frequency divider. The final stage is provided with the forward part of the phase-locked loop connected to a different fixed frequency divider for performing feedback through the fixed frequency divider. By changing the frequency division constant of the variable frequency divider of a circuit, fine frequency adjustment is performed at a very high speed. The accuracy of the adjustment depends on the relative value of the frequency divider and the number of the intermediate stages inside a system.

公开(公告)号：JP2000250883A

公开(公告)日：2000-09-14

申请号：JP2000045925

申请日：2000-02-23

Applicant: IBM

Inventor： JOHN PATON BANNISTER ,  CARPENTER GARY DALE ,  MARK EDWARD DEAN ,  DAVID BRIAN GRASCO ,  RICHARD NICHOLAS IACHETTA JR

IPC: G06F12/08 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To avoid the loss of data and coherence by respectively providing first and second nodes with a local mutual connection, a system memory coupled with the local mutual connection and a node controller located between the local mutual connections. SOLUTION: A READ request in a home node 10a is transferred to a remote node 10b where corrected data are resident. Concerning the READ request, the boat of correction/intervention is received by the remote node 10b. The remote node 10b returns the corrected/intervened boat and the corrected data to the home node 10a. A node controller 20 generates a new tag and issue the write back kill (WBC request) of R bit = 1. A coherence mechanism in the node controller 20 completes the WBC request like ReRum of locally generated WBC requests. In this case, data in a local memory 18 are made effective.

公开(公告)号：JP2000242621A

公开(公告)日：2000-09-08

申请号：JP2000031050

申请日：2000-02-08

Applicant: IBM

Inventor： CARPENTER GARY D ,  MARK EDWARD DEAN ,  DAVID BRIAN GLASCO

IPC: G06F12/08 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To reduce the number of readout requests and wait time of the nonuniform memory access computer system by interposing a 1st cache hierarchy in common and using only communication through local interconnection, and sending a copy of a specific cache line to a 2nd cache hierarchy. SOLUTION: When the 1st cache hierarchy 14 as a request source receives a request cache line through local interconnection 16, a cache controller of the 2nd cache hierarchy 14 caches the request cache line and sets its coherence state to a (Recent) state. Namely, the 1st cache hierarchy 14 as the request source among local cache hierarchy 14 holding the request cache line is interposed in common and only the communication by the local interconnection 16 is used to send a copy of the specific cache line to the 2nd cache hierarchy 14.