公开(公告)号：SG44431A1

公开(公告)日：1997-12-19

申请号：SG1996000365

申请日：1990-05-16

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  MILLING PHILIP E

IPC: G06F12/08

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：NZ233538A

公开(公告)日：1992-06-25

申请号：NZ23353890

申请日：1990-05-02

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08 ,  G06F13/16

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：AU5506690A

公开(公告)日：1990-12-06

申请号：AU5506690

申请日：1990-05-15

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.