公开(公告)号：CA2107056A1

公开(公告)日：1994-07-09

申请号：CA2107056

申请日：1993-09-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  MUHICH JOHN S ,  OEHLER RICHARD R ,  SILHA EDWARD J

IPC: G06F15/16 ,  G06F12/10 ,  G06F15/177

Abstract: A method and system for increasing memory concurrency in a multiprocessor computer system where each processor includs an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields. A reference bit is provided within a first individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bit in separate individually accessible fields the reference bit and change bit may be concurrently updated by multiple processors.