公开(公告)号：JP2006309766A

公开(公告)日：2006-11-09

申请号：JP2006122694

申请日：2006-04-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MCINTOSH GORDON D ,  SILHA EDWARD J

IPC: G06F21/22 ,  G09C1/00

CPC classification number: G06F21/57 ,  G06F9/30178 ,  G06F9/3802 ,  G06F21/71 ,  G06F21/72 ,  G06F21/85

Abstract: PROBLEM TO BE SOLVED: To provide a method for an operating system for preventing computer attack, which cannot be prevented conventionally. SOLUTION: This method includes a step for fetching an encrypted architecturization instruction, a step for separating the encrypted architecturization instruction into one or more encrypted operation codes and a set of instruction bits, a decryption step for decrypting the encrypted operation code by using one of a plurality of modes for forming one or more decrypted operation codes, a combination step for combining the decrypted operation code and the set of instruction bits for forming a decrypted architecturization instruction, and a step for transferring the decrypted architecturization instruction to an instruction execution unit. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于防止计算机攻击的操作系统的方法，这种传统方法是不能防止的。 解决方案：该方法包括用于获取加密的架构化指令的步骤，将加密的架构化指令分离为一个或多个加密的操作码和一组指令比特的步骤，用于通过使用解密步骤对加密的操作码进行解密的解密步骤 用于形成一个或多个解密的操作码的多种模式之一，用于组合解密的操作码和用于形成解密的架构化指令的指令位组合的组合步骤，以及用于将解密的架构化指令传送到指令执行的步骤 单元。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：CA2123447A1

公开(公告)日：1995-03-21

申请号：CA2123447

申请日：1994-05-12

Applicant: IBM

Inventor： ARNDT RICHARD L ,  NICHOLSON JAMES O ,  SILHA EDWARD J ,  THURBER STEVEN M ,  YOUNGS AMY M

IPC: G06F15/16 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/177

Abstract: An interrupt subsystem within a data processing system is scalable from low-end uniprocessor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queuing of interrupts from many sources, and for queuing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.

公开(公告)号：DE69322244T2

公开(公告)日：1999-07-01

申请号：DE69322244

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  MUHICH JOHN S ,  OEHLER RICHARD R ,  SILHA EDWARD J

IPC: G06F15/16 ,  G06F12/10 ,  G06F15/177 ,  G06F12/12

Abstract: A method and system for increasing memory concurrency in a multiprocessor computer system where each processor includs an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields. A reference bit is provided within a first individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bit in separate individually accessible fields the reference bit and change bit may be concurrently updated by multiple processors.

公开(公告)号：DE69322244D1

公开(公告)日：1999-01-07

申请号：DE69322244

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  MUHICH JOHN S ,  OEHLER RICHARD R ,  SILHA EDWARD J

IPC: G06F15/16 ,  G06F12/10 ,  G06F15/177 ,  G06F12/12

Abstract: A method and system for increasing memory concurrency in a multiprocessor computer system where each processor includs an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields. A reference bit is provided within a first individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bit in separate individually accessible fields the reference bit and change bit may be concurrently updated by multiple processors.

公开(公告)号：CA2107056A1

公开(公告)日：1994-07-09

申请号：CA2107056

申请日：1993-09-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  MUHICH JOHN S ,  OEHLER RICHARD R ,  SILHA EDWARD J

IPC: G06F15/16 ,  G06F12/10 ,  G06F15/177

Abstract: A method and system for increasing memory concurrency in a multiprocessor computer system where each processor includs an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields. A reference bit is provided within a first individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bit in separate individually accessible fields the reference bit and change bit may be concurrently updated by multiple processors.