公开(公告)号：JP2004348734A

公开(公告)日：2004-12-09

申请号：JP2004148226

申请日：2004-05-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DAY MICHAEL N ,  JOHNS CHARLES R ,  KAHLE JAMES A ,  LIU PEICHUM P ,  TRUONG THUONG QUANG

IPC: G06F12/08 ,  G06F9/46 ,  G06F13/14 ,  G06F13/28 ,  G06F15/177

CPC classification number: G06F13/28 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0831 ,  G06F2213/0038

Abstract: PROBLEM TO BE SOLVED: To provide a method for providing an atomic update primitive into an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfer. SOLUTION: At least one lock line command is generated from a set including a reserved Get Lock Line command, a Put Lock Line Conditional command, and an unconditional Put Lock Line command. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2007122741A

公开(公告)日：2007-05-17

申请号：JP2006334314

申请日：2006-12-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DAY MICHAEL N ,  JOHNS CHARLES R ,  KAHLE JAMES A ,  LIU PEICHUM P ,  TRUONG THUONG QUANG

IPC: G06F9/52 ,  G06F12/08 ,  G06F9/46 ,  G06F13/14 ,  G06F13/28 ,  G06F15/167

CPC classification number: G06F13/28 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0831 ,  G06F2213/0038

Abstract: PROBLEM TO BE SOLVED: To provide for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. SOLUTION: At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command and a put lock line unconditional command. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有DMA传输的共享存储器的非对称单芯片异构多处理器计算机系统中的原子更新原语。

解决方案：从包含预留的get lock line命令，put lock line条件命令和put lock line无条件命令的集合中生成至少一个lock line命令。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：DE69325566D1

公开(公告)日：1999-08-12

申请号：DE69325566

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

IPC: G06F9/38

公开(公告)号：CA2107306A1

公开(公告)日：1994-07-09

申请号：CA2107306

申请日：1993-09-29

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  TU PAUL K ,  WALDECKER DONALD E

IPC: G06F9/38 ,  G06F15/16

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register or a designated alternate general purpose register.

公开(公告)号：CA2245106C

公开(公告)日：2002-08-06

申请号：CA2245106

申请日：1998-08-14

Applicant: IBM

Inventor： TRAN CANG N ,  KAHLE JAMES A

IPC: G06F13/40 ,  G06F15/17 ,  G06F15/167

Abstract: A method and system for input/output control in a multiprocessor system havi ng multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously in response to one or more transfer requests. In response to a transfer request having a data address associated therewith, a particular target devi ce is identified. The data address is then written into an address queue. Thereafter, one or m ore of the multiple sub-buses are utilized to transfer data to or from a single process or in response to a transfer request from a single processor. In response to a transfer req uest from multiple processors, one or more of the multiple sub-buses may be utilized s eparately to simultaneously transfer data to or from multiple processors.

公开(公告)号：AT182013T

公开(公告)日：1999-07-15

申请号：AT93120931

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

IPC: G06F9/38

公开(公告)号：CA2245106A1

公开(公告)日：1999-03-18

申请号：CA2245106

申请日：1998-08-14

Applicant: IBM

Inventor： TRAN CANG N ,  KAHLE JAMES A

IPC: G06F13/40 ,  G06F15/17 ,  G06F15/167

Abstract: A method and system for input/output control in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wid e bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple pro cessors simultaneously in response to one or more transfer requests. In response to a tr ansfer request having a data address associated therewith, a particular target device i s identified. The data address is then written into an address queue. Thereafter, one or more of the multiple sub-buses are utilized to transfer data to or from a single processor i n response to a transfer request from a single processor. In response to a transfer request from multiple processors, one or more of the multiple sub-buses may be utilized separ ately to simultaneously transfer data to or from multiple processors.

公开(公告)号：CA2245633C

公开(公告)日：2002-08-06

申请号：CA2245633

申请日：1998-08-14

Applicant: IBM

Inventor： TRAN CANG N ,  KAHLE JAMES A

IPC: G06F13/364 ,  G06F15/167

Abstract: A method and system for enhanced bus access in a multiprocessor system havin g multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously. In response to one or more pending transactions, each proces sor outputs a request to bus arbitration logic for a maximum-permitted number of sub-bus es. If the number of sub-buses granted to a particular processor equals the number of p ending transactions at that processor, all pending transactions are performed in pa rallel on separate sub-buses. If the number of sub-buses granted is less than the numb er of pending transactions, pending transactions are performed in a priority order . Finally, if the number of granted sub-buses is greater than the number of pending transactio ns, selected transactions are performed over multiple sub-buses in parallel, greatly enha ncing the speed of those transactions.

公开(公告)号：DE69325566T2

公开(公告)日：2000-01-27

申请号：DE69325566

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

IPC: G06F9/38

公开(公告)号：DE69322244T2

公开(公告)日：1999-07-01

申请号：DE69322244

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  MUHICH JOHN S ,  OEHLER RICHARD R ,  SILHA EDWARD J

IPC: G06F15/16 ,  G06F12/10 ,  G06F15/177 ,  G06F12/12

Abstract: A method and system for increasing memory concurrency in a multiprocessor computer system where each processor includs an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields. A reference bit is provided within a first individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bit in separate individually accessible fields the reference bit and change bit may be concurrently updated by multiple processors.