公开(公告)号：SG50865A1

公开(公告)日：1998-07-20

申请号：SG1997002418

申请日：1997-07-09

Applicant: IBM ,  SIEMENS AG

Inventor： HAUF MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

IPC: H01L27/08 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/105

Abstract: An integrated circuit with FETs having an essentially uniform gate oxide thickness and FETs having gate oxide thickness enhanced along the sides. FETs with enhanced gate oxide have an ONO layer (126) diffused with Potassium in close proximity to the enhanced (thicker) oxide, and, as a result, have a slightly higher Vt and much more attenuated soft turn on.

公开(公告)号：DE69738059T2

公开(公告)日：2008-05-21

申请号：DE69738059

申请日：1997-07-15

Applicant: SIEMENS AG ,  IBM

Inventor： HAUF MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

IPC: H01L21/76 ,  H01L21/763 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/78

Abstract: An FET isolated on either side by a trench. The FET has a dielectric layer in the isolating trench along at least one side. The dielectric layer which may be an ONO layer has an oxidation catalyst diffused into it. The oxidation catalyst may be potassium. Gate oxide along the side of the FET in close proximity to the ONO layer is thicker than gate oxide between both sides.

公开(公告)号：DE69712138T2

公开(公告)日：2003-01-30

申请号：DE69712138

申请日：1997-07-14

Applicant: IBM ,  SIEMENS AG

Inventor： HAUF MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

IPC: H01L27/08 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/088

Abstract: An integrated circuit with FETs having an essentially uniform gate oxide thickness and FETs having gate oxide thickness enhanced along the sides. FETs with enhanced gate oxide have an ONO layer (126) diffused with Potassium in close proximity to the enhanced (thicker) oxide, and, as a result, have a slightly higher Vt and much more attenuated soft turn on.

公开(公告)号：DE3751732T2

公开(公告)日：1996-09-26

申请号：DE3751732

申请日：1987-03-24

Applicant: IBM

Inventor： FULTON INGE GRUMM ,  MAKRIS JAMES STEVE ,  NASTASI VICTOR RAY ,  SCADUTO ANTHONY FRANCIS ,  SHARTEL ANNE CHARLENE

IPC: H01L21/76 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/31

Abstract: Disclosed is a process of growing a conformal and etch-resistant silicon dioxide on a surface by forming a conformal layer of polysilicon and subjecting the polysilicon to thermal oxidation to completely convert the polysilicon into (poly) silicon oxide. Disclosed also is a method of forming an isolation trench in a semiconductor substrate having a high integrity oxide sidewall. After forming the trench (58) in the substrate surface using a suitable etch mask and RIE, a single (thermal) oxide or dual (thermal) oxide and (CVD) nitride liner (64) is formed on all trench surfaces. A conformal layer of undoped polysilicon (66) is then formed (by. e.g. LPCVD) on the liner. By subjecting to thermal oxidation, the polysilicon is completely converted into a conformal (poly) silicon oxide layer (68) having a thickness about 2.5 times that of the polysilicon layer. The resulting (poly) silicon oxide has the conformality of CVD oxide and the high etch resistance of thermally grown oxide. Alternatively, prior to forming the (poly) silicon oxide, the polysilicon layer is removed from the trench floor and the substrate surface in order to limit volume expansion of the polysilicon to a single direction perpendicular to the trench walls. The trench is filled with oxide, epitaxial silicon, polysilicon, polymers or metal, as desired. For achieving substrate contact through the trench, the trench bottom is opened up by RIE. Polysilicon is deposited with in-situ doping at a high temperature to fill the trench and simultaneously diffuse the dopant from the polysilicon fill into the underlying substrate to form a channel stop.

公开(公告)号：DE3751732D1

公开(公告)日：1996-04-18

申请号：DE3751732

申请日：1987-03-24

Applicant: IBM

Inventor： FULTON INGE GRUMM ,  MAKRIS JAMES STEVE ,  NASTASI VICTOR RAY ,  SCADUTO ANTHONY FRANCIS ,  SHARTEL ANNE CHARLENE

IPC: H01L21/76 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/31

Abstract: Disclosed is a process of growing a conformal and etch-resistant silicon dioxide on a surface by forming a conformal layer of polysilicon and subjecting the polysilicon to thermal oxidation to completely convert the polysilicon into (poly) silicon oxide. Disclosed also is a method of forming an isolation trench in a semiconductor substrate having a high integrity oxide sidewall. After forming the trench (58) in the substrate surface using a suitable etch mask and RIE, a single (thermal) oxide or dual (thermal) oxide and (CVD) nitride liner (64) is formed on all trench surfaces. A conformal layer of undoped polysilicon (66) is then formed (by. e.g. LPCVD) on the liner. By subjecting to thermal oxidation, the polysilicon is completely converted into a conformal (poly) silicon oxide layer (68) having a thickness about 2.5 times that of the polysilicon layer. The resulting (poly) silicon oxide has the conformality of CVD oxide and the high etch resistance of thermally grown oxide. Alternatively, prior to forming the (poly) silicon oxide, the polysilicon layer is removed from the trench floor and the substrate surface in order to limit volume expansion of the polysilicon to a single direction perpendicular to the trench walls. The trench is filled with oxide, epitaxial silicon, polysilicon, polymers or metal, as desired. For achieving substrate contact through the trench, the trench bottom is opened up by RIE. Polysilicon is deposited with in-situ doping at a high temperature to fill the trench and simultaneously diffuse the dopant from the polysilicon fill into the underlying substrate to form a channel stop.

公开(公告)号：BR8702320A

公开(公告)日：1988-02-17

申请号：BR8702320

申请日：1987-05-06

Applicant: IBM

Inventor： FULTON INGE GRUMM ,  MAKRIS JAMES STEVE ,  NASTASI VICTOR RAY ,  SCADUTO ANTHONY FRANCIS ,  SHARTEL ANNE CHARLENE

IPC: H01L21/76 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/316

Abstract: Disclosed is a process of growing a conformal and etch-resistant silicon dioxide on a surface by forming a conformal layer of polysilicon and subjecting the polysilicon to thermal oxidation to completely convert the polysilicon into (poly) silicon oxide. Disclosed also is a method of forming an isolation trench in a semiconductor substrate having a high integrity oxide sidewall. After forming the trench (58) in the substrate surface using a suitable etch mask and RIE, a single (thermal) oxide or dual (thermal) oxide and (CVD) nitride liner (64) is formed on all trench surfaces. A conformal layer of undoped polysilicon (66) is then formed (by. e.g. LPCVD) on the liner. By subjecting to thermal oxidation, the polysilicon is completely converted into a conformal (poly) silicon oxide layer (68) having a thickness about 2.5 times that of the polysilicon layer. The resulting (poly) silicon oxide has the conformality of CVD oxide and the high etch resistance of thermally grown oxide. Alternatively, prior to forming the (poly) silicon oxide, the polysilicon layer is removed from the trench floor and the substrate surface in order to limit volume expansion of the polysilicon to a single direction perpendicular to the trench walls. The trench is filled with oxide, epitaxial silicon, polysilicon, polymers or metal, as desired. For achieving substrate contact through the trench, the trench bottom is opened up by RIE. Polysilicon is deposited with in-situ doping at a high temperature to fill the trench and simultaneously diffuse the dopant from the polysilicon fill into the underlying substrate to form a channel stop.