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    INTEGRATED CIRCUIT CHIP
    1.
    发明专利
    INTEGRATED CIRCUIT CHIP 失效

    公开(公告)号：JPH1074912A

    公开(公告)日：1998-03-17

    申请号：JP21707897

    申请日：1997-07-28

    Applicant: IBM ,  SIEMENS AG

    Inventor： HAUF MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

    IPC: H01L27/08 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To selectively reduce a leakage of an FET channel by making a gate oxide along the side of a second FET located extremely near to an ONO layer and thicker than a gate oxide between both FET sides. SOLUTION: In order to separately define an FET region 124, a trench 120 is etched inside a wafer 122 passing through a pad stack. An ONO layer 126 is formed in the common shape on the pad stack and inside the trench 120. A polysilicon layer is removed from the upper part of the pad stack, so that only polysilicon 132 may remain inside the trench 120. An oxide collar 134 is selectively formed inside the trench 120 along the ONO layer 126 on the polysilicon 132. The polysilicon layer is removed from the pad stack, so that polysilicon 140 remains only inside the trench 120. Then, the part along the side 142 of a channel, that is the part extremely close to the ONO layer 126, results in having a thicker gate oxide.

    MANUFACTURE OF INSULATED GATE FIELD-EFFECT TRANSISTOR
    2.
    发明专利
    MANUFACTURE OF INSULATED GATE FIELD-EFFECT TRANSISTOR 失效

    公开(公告)号：JPH10107227A

    公开(公告)日：1998-04-24

    申请号：JP21707797

    申请日：1997-07-28

    Applicant: IBM ,  SIEMENS AG

    Inventor： HAUE MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

    IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To reduce a leakage of an FET channel by diffusing potassium along an ONO layer backing a trench on the surface of a wafer and forming a gate oxide on the exposed wafer surface. SOLUTION: A trench 120 is etched in a wafer 122 through a pad stack 121, a channel, a source, and a drain are formed in an FET region 124 defined above, and an ONO layer 126 backs the trench 120, passes through the surface 128 of the wafer 122 and extends on both sides of each trench 120 along the pad stack 121. An N polysilicon layer 130 is deposited on the ONO layer 126 and is removed so that polysilicon 132 is remained only in the trench 120, and the polysilicon layer 126 is polished to remove the residual ONO layer 124 from the pad stack 121. Consequently, by etching so that the polysilicon 132 remained in the trench is recessed from the surface 128, the FET in which a leakage of a channel is minimized can be formed.

    A method of manufacturing an insulated gate field effect transistor
    4.
    发明专利
    A method of manufacturing an insulated gate field effect transistor 未知

    公开(公告)号：SG50863A1

    公开(公告)日：1998-07-20

    申请号：SG1997002379

    申请日：1997-07-07

    Applicant: IBM ,  SIEMENS AG

    Inventor： HAUF MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

    IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L27/105

    Abstract: A Field Effect Transistor (FET) and a method of forming FETs on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. Gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide. Preferably, potassium is introduced during Chem-Mech polish when the trenches are filled with polysilicon. A slurry containing KOH is used to polish the polysilicon and the potassium diffuses from the slurry along the ONO layer. After chem-Mech polish, the poly in the trenches is recessed by Reactive Ion Etching (RIE) it below the wafer surface. Optionally, after RIE, the wafer may be dipped in a KOH solution. Next, an oxide collar is formed along the ONO layer in the trenches above the recessed polysilicon. The recesses are filled by a second layer of polysilicon that is Chem-Mech polished with the same slurry to remove polysilicon from the wafer surface. The polished polysilicon may be Reactive Ion etched until it is essentially coplanar with the wafer surface. The resulting FET has thicker gate oxide along its sides than in the center of its channel.

    6.
    发明专利
    未知

    公开(公告)号：DE69737172T2

    公开(公告)日：2008-01-03

    申请号：DE69737172

    申请日：1997-07-15

    Applicant: SIEMENS AG ,  IBM

    Inventor： HAUE MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

    IPC: H01L21/8242 ,  H01L29/78 ,  H01L21/306 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/108 ,  H01L29/423

    Abstract: A Field Effect Transistor (FET) and a method of forming FETs on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. Gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide. Preferably, potassium is introduced during Chem-Mech polish when the trenches are filled with polysilicon. A slurry containing KOH is used to polish the polysilicon and the potassium diffuses from the slurry along the ONO layer. After chem-Mech polish, the poly in the trenches is recessed by Reactive Ion Etching (RIE) it below the wafer surface. Optionally, after RIE, the wafer may be dipped in a KOH solution. Next, an oxide collar is formed along the ONO layer in the trenches above the recessed polysilicon. The recesses are filled by a second layer of polysilicon that is Chem-Mech polished with the same slurry to remove polysilicon from the wafer surface. The polished polysilicon may be Reactive Ion etched until it is essentially coplanar with the wafer surface. The resulting FET has thicker gate oxide along its sides than in the center of its channel.

    7.
    发明专利
    未知

    公开(公告)号：DE69737172D1

    公开(公告)日：2007-02-15

    申请号：DE69737172

    申请日：1997-07-15

    Applicant: SIEMENS AG ,  IBM

    Inventor： HAUE MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

    IPC: H01L21/8242 ,  H01L29/78 ,  H01L21/306 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/108 ,  H01L29/423

    Abstract: A Field Effect Transistor (FET) and a method of forming FETs on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. Gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide. Preferably, potassium is introduced during Chem-Mech polish when the trenches are filled with polysilicon. A slurry containing KOH is used to polish the polysilicon and the potassium diffuses from the slurry along the ONO layer. After chem-Mech polish, the poly in the trenches is recessed by Reactive Ion Etching (RIE) it below the wafer surface. Optionally, after RIE, the wafer may be dipped in a KOH solution. Next, an oxide collar is formed along the ONO layer in the trenches above the recessed polysilicon. The recesses are filled by a second layer of polysilicon that is Chem-Mech polished with the same slurry to remove polysilicon from the wafer surface. The polished polysilicon may be Reactive Ion etched until it is essentially coplanar with the wafer surface. The resulting FET has thicker gate oxide along its sides than in the center of its channel.

    8.
    发明专利
    未知

    公开(公告)号：ES2084575T3

    公开(公告)日：1996-05-16

    申请号：ES87104307

    申请日：1987-03-24

    Applicant: IBM

    Inventor： FULTON INGE GRUMM ,  MAKRIS JAMES STEVE ,  NASTASI VICTOR RAY ,  SCADUTO ANTHONY FRANCIS ,  SHARTEL ANNE CHARLENE

    IPC: H01L21/76 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/31

    Abstract: Disclosed is a process of growing a conformal and etch-resistant silicon dioxide on a surface by forming a conformal layer of polysilicon and subjecting the polysilicon to thermal oxidation to completely convert the polysilicon into (poly) silicon oxide. Disclosed also is a method of forming an isolation trench in a semiconductor substrate having a high integrity oxide sidewall. After forming the trench (58) in the substrate surface using a suitable etch mask and RIE, a single (thermal) oxide or dual (thermal) oxide and (CVD) nitride liner (64) is formed on all trench surfaces. A conformal layer of undoped polysilicon (66) is then formed (by. e.g. LPCVD) on the liner. By subjecting to thermal oxidation, the polysilicon is completely converted into a conformal (poly) silicon oxide layer (68) having a thickness about 2.5 times that of the polysilicon layer. The resulting (poly) silicon oxide has the conformality of CVD oxide and the high etch resistance of thermally grown oxide. Alternatively, prior to forming the (poly) silicon oxide, the polysilicon layer is removed from the trench floor and the substrate surface in order to limit volume expansion of the polysilicon to a single direction perpendicular to the trench walls. The trench is filled with oxide, epitaxial silicon, polysilicon, polymers or metal, as desired. For achieving substrate contact through the trench, the trench bottom is opened up by RIE. Polysilicon is deposited with in-situ doping at a high temperature to fill the trench and simultaneously diffuse the dopant from the polysilicon fill into the underlying substrate to form a channel stop.

    10.
    发明专利
    未知

    公开(公告)号：DE69712138D1

    公开(公告)日：2002-05-29

    申请号：DE69712138

    申请日：1997-07-14

    Applicant: IBM ,  SIEMENS AG

    Inventor： HAUF MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

    IPC: H01L27/08 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/088

    Abstract: An integrated circuit with FETs having an essentially uniform gate oxide thickness and FETs having gate oxide thickness enhanced along the sides. FETs with enhanced gate oxide have an ONO layer (126) diffused with Potassium in close proximity to the enhanced (thicker) oxide, and, as a result, have a slightly higher Vt and much more attenuated soft turn on.

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