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    4.
    发明专利
    未知

    公开(公告)号：ES2084575T3

    公开(公告)日：1996-05-16

    申请号：ES87104307

    申请日：1987-03-24

    Applicant: IBM

    Inventor： FULTON INGE GRUMM ,  MAKRIS JAMES STEVE ,  NASTASI VICTOR RAY ,  SCADUTO ANTHONY FRANCIS ,  SHARTEL ANNE CHARLENE

    IPC: H01L21/76 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/31

    Abstract: Disclosed is a process of growing a conformal and etch-resistant silicon dioxide on a surface by forming a conformal layer of polysilicon and subjecting the polysilicon to thermal oxidation to completely convert the polysilicon into (poly) silicon oxide. Disclosed also is a method of forming an isolation trench in a semiconductor substrate having a high integrity oxide sidewall. After forming the trench (58) in the substrate surface using a suitable etch mask and RIE, a single (thermal) oxide or dual (thermal) oxide and (CVD) nitride liner (64) is formed on all trench surfaces. A conformal layer of undoped polysilicon (66) is then formed (by. e.g. LPCVD) on the liner. By subjecting to thermal oxidation, the polysilicon is completely converted into a conformal (poly) silicon oxide layer (68) having a thickness about 2.5 times that of the polysilicon layer. The resulting (poly) silicon oxide has the conformality of CVD oxide and the high etch resistance of thermally grown oxide. Alternatively, prior to forming the (poly) silicon oxide, the polysilicon layer is removed from the trench floor and the substrate surface in order to limit volume expansion of the polysilicon to a single direction perpendicular to the trench walls. The trench is filled with oxide, epitaxial silicon, polysilicon, polymers or metal, as desired. For achieving substrate contact through the trench, the trench bottom is opened up by RIE. Polysilicon is deposited with in-situ doping at a high temperature to fill the trench and simultaneously diffuse the dopant from the polysilicon fill into the underlying substrate to form a channel stop.

    6.
    发明专利
    未知

    公开(公告)号：DE3586554D1

    公开(公告)日：1992-10-01

    申请号：DE3586554

    申请日：1985-06-03

    Applicant: IBM

    Inventor： GOTH GEORGE RICHARD ,  HANSEN THOMAS ADRIAN ,  MAKRIS JAMES STEVE

    IPC: H01L21/761 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L29/41

    Abstract: Deep trenches (14, 15) are formed according to the desired pattern through the N epitaxial layer (13) and N + subcollector region (12) into the P- substrate (11) of a silicon structure (10). Where a substrate contact is needed, the trenches delineate a central stud (16) or mesa of silicon material. Channel stop regions (18) are formed e.g. by ion implantation of boron atoms at the bottom of trenches. Si0 2 and Si 3 N 4 layers (17, 19) are then deposited on the whole structure. A substrate contact mask is applied and patterned to selectively expose one side of the trench sidewalls, the bottom of the trenches adjacent thereto and others areas if desired such as the top surface of the stud. The composite SiO 2 /Si 3 N 4 layer is then etched to leave exposed only the sidewalls of the stud, at least partially the bottom of the trenches adjacent thereto and the top surface of the stud. Platinum is deposited preferably via sputter deposition, conformally coating all regions of the structure. After sintering, the unreacted platinum is removed using wet chemical etch (aqua regia). Platinum silicide is left in all opened contacts and on the stud sidewalls where its defines a metal silicide lining (25) or cap, covering the stud. This lining connects the top surface (25a) of the stud, with the channel stop implanted regions (18) and thence forms the desired substrate contact.

    7.
    发明专利
    未知

    公开(公告)号：IT1149957B

    公开(公告)日：1986-12-10

    申请号：IT2199580

    申请日：1980-05-13

    Applicant: IBM

    Inventor： BARILE CONRAD ALBERT ,  GOTH GEORGE RICHARD ,  MAKRIS JAMES STEVE ,  NAGARAJAN ARUNACHALA ,  RAHEJA RAJ KANWAL

    IPC: H01L29/73 ,  H01L21/033 ,  H01L21/265 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/07 ,  H01L29/417

    Abstract: A very high current ion implanted emitter is formed in a diffused base. Windows are made through the silicon nitride and silicon dioxide layes to both the base contact and the emitter regions using a resist mask. These regions are then protected by resist and the collector contact window is opened through the remainder of the silicon dioxide layer to the reach through region. A screen oxide is then grown in all the exposed areas after the removal of the resist mask. A resist mask is applied which covers only the base and Schottky anode regions. Arsenic is then implanted through the exposed screened areas followed by an etch back step to remove the top damaged layer. With some remaining screen oxide serving as a cap, the emitter drive-in is done.

    8.
    发明专利
    未知

    公开(公告)号：DE3586554T2

    公开(公告)日：1993-04-08

    申请号：DE3586554

    申请日：1985-06-03

    Applicant: IBM

    Inventor： GOTH GEORGE RICHARD ,  HANSEN THOMAS ADRIAN ,  MAKRIS JAMES STEVE

    IPC: H01L21/761 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L29/41

    Abstract: Deep trenches (14, 15) are formed according to the desired pattern through the N epitaxial layer (13) and N + subcollector region (12) into the P- substrate (11) of a silicon structure (10). Where a substrate contact is needed, the trenches delineate a central stud (16) or mesa of silicon material. Channel stop regions (18) are formed e.g. by ion implantation of boron atoms at the bottom of trenches. Si0 2 and Si 3 N 4 layers (17, 19) are then deposited on the whole structure. A substrate contact mask is applied and patterned to selectively expose one side of the trench sidewalls, the bottom of the trenches adjacent thereto and others areas if desired such as the top surface of the stud. The composite SiO 2 /Si 3 N 4 layer is then etched to leave exposed only the sidewalls of the stud, at least partially the bottom of the trenches adjacent thereto and the top surface of the stud. Platinum is deposited preferably via sputter deposition, conformally coating all regions of the structure. After sintering, the unreacted platinum is removed using wet chemical etch (aqua regia). Platinum silicide is left in all opened contacts and on the stud sidewalls where its defines a metal silicide lining (25) or cap, covering the stud. This lining connects the top surface (25a) of the stud, with the channel stop implanted regions (18) and thence forms the desired substrate contact.

    9.
    发明专利
    未知

    公开(公告)号：DE2531003A1

    公开(公告)日：1976-02-05

    申请号：DE2531003

    申请日：1975-07-11

    Applicant: IBM DEUTSCHLAND

    Inventor： KOENIG WILFRIED GUSTAF ,  MAKRIS JAMES STEVE ,  MASTERS BURTON JOSEPH

    IPC: H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L21/74

    Abstract: A method of ion implantation into a semiconductor substrate which comprises forming a layer of an electrically insulative material, such as silicon dioxide, on the substrate over the region to be ion implanted. Then, a beam of ions having sufficient energy to pass through the layer of insulative material and to penetrate into the substrate is directed at a particular portion of the insulative layer. Before proceeding further, at least the upper half of the insulative layer, and preferably all of the upper portion of the insulative layer, in excess of a remaining thickness of 100A, is removed by etching. Then, the substrate is heated whereby the ions are driven further into the substrate to form the selected ion implanted region.

    10.
    发明专利
    未知

    公开(公告)号：DE3751732T2

    公开(公告)日：1996-09-26

    申请号：DE3751732

    申请日：1987-03-24

    Applicant: IBM

    Inventor： FULTON INGE GRUMM ,  MAKRIS JAMES STEVE ,  NASTASI VICTOR RAY ,  SCADUTO ANTHONY FRANCIS ,  SHARTEL ANNE CHARLENE

    IPC: H01L21/76 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/31

    Abstract: Disclosed is a process of growing a conformal and etch-resistant silicon dioxide on a surface by forming a conformal layer of polysilicon and subjecting the polysilicon to thermal oxidation to completely convert the polysilicon into (poly) silicon oxide. Disclosed also is a method of forming an isolation trench in a semiconductor substrate having a high integrity oxide sidewall. After forming the trench (58) in the substrate surface using a suitable etch mask and RIE, a single (thermal) oxide or dual (thermal) oxide and (CVD) nitride liner (64) is formed on all trench surfaces. A conformal layer of undoped polysilicon (66) is then formed (by. e.g. LPCVD) on the liner. By subjecting to thermal oxidation, the polysilicon is completely converted into a conformal (poly) silicon oxide layer (68) having a thickness about 2.5 times that of the polysilicon layer. The resulting (poly) silicon oxide has the conformality of CVD oxide and the high etch resistance of thermally grown oxide. Alternatively, prior to forming the (poly) silicon oxide, the polysilicon layer is removed from the trench floor and the substrate surface in order to limit volume expansion of the polysilicon to a single direction perpendicular to the trench walls. The trench is filled with oxide, epitaxial silicon, polysilicon, polymers or metal, as desired. For achieving substrate contact through the trench, the trench bottom is opened up by RIE. Polysilicon is deposited with in-situ doping at a high temperature to fill the trench and simultaneously diffuse the dopant from the polysilicon fill into the underlying substrate to form a channel stop.

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