公开(公告)号：CA1228425A

公开(公告)日：1987-10-20

申请号：CA478628

申请日：1985-04-09

Applicant: IBM

Inventor： LU NICKY C ,  NING TAK H ,  TERMAN LEWIS M

IPC: H01L27/10 ,  G11C11/34 ,  G11C11/40 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: DYNAMIC RAM CELL WITH MOS TRENCH CAPACITOR IN CMOS This invention relates generally to Dynamic Random Access Memory (DRAM) cells and more particularly relates to a DRAM cell wherein the storage capacitor of the cell is disposed in a trench formed in a semiconductor substrate. Still more particularly, it relates to a DRAM cell wherein at least a portion of the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench capacitor forms the other electrode of the storage capacitor. The DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the substrate. The well itself is formed in a lightly doped portion of the substrate and may be n or p-type conductivity with the other portions of the cell having conductivity types appropriate for devices fabricated in the CMOS environment. The trench capacitor extends from the surface of the well through the well and lightly doped substrate portion into the heavily doped portion of the substrate. The electrode disposed in the trench is directly connected to the source/drain of the access transistor.

公开(公告)号：CA1142261A

公开(公告)日：1983-03-01

申请号：CA349766

申请日：1980-04-14

Applicant: IBM

Inventor： NING TAK H ,  WIEDMANN SIEGFRIED K

IPC: H01L21/8222 ,  H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/06 ,  H01L29/43 ,  H01L21/44

Abstract: A technique for making ohmic electrical interconnections between semiconductor regions of opposite conductivity type, without requiring metallic interconnection lines. This technique has applicability in any circuit using bipolar devices, and in particular is useful to provide a very dense static memory array of bipolar transistors, To join the opposite conductivity regions, intermediate layers are formed including a silicide of a refractory metal, such as W, Mo, Ta, etc. and at least one layer of doped polycrystalline silicon having M and P type regions, the refractory metal silicide forms an electrical connection to at least one doped polysilicon layer of a first conductivity type and to either a single crystal semiconductor region of the opposite conductivity type or to another polysilicon layer which also has the opposite conductivity type. As an example, an N type silicon region is interconnected to a P type silicon region by intermediate layers of N pol licon - refractory metal silicide - P polysilicon.

公开(公告)号：CA1118534A

公开(公告)日：1982-02-16

申请号：CA326907

申请日：1979-05-02

Applicant: IBM

Inventor： NING TAK H ,  YU HWA N

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/285 ,  H01L21/331

Abstract: METHODS FOR FABRICATING SELF-ALIGNED BIPOLAR TRANSISTORS HAVING POLYSILICON BASE CONTACTS WITH POLYSILICON OR METAL EMITTER CONTACTS A method consisting of a sequence of process steps for fabricating a bipolar transistor having base contacts formed of polysilicon material and an emitter contact formed of polysilicon material or metal. The emitter contact is self-aligned to the base contacts by the use of process steps wherein a single mask aperture is used for defining the base contacts and the emitter. YO977-058