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公开(公告)号：US3588830A
公开(公告)日：1971-06-28
申请号：US3588830D
申请日：1968-01-17
Applicant: IBM
Inventor： DUDA WILLIAM J , TERMAN LEWIS M
CPC classification number: G11C29/70
Abstract: A SYSTEM IS SET FORTH FOR UTILIZING BATCH FABRICATED MEMORIES DESPITE THE PRESENCE OF PERMANENTLY UNUSABLE BITS IN SUCH MEMORIES. IN ADDITION TO A MAIN BULK MEMORY, THERE IS PROVIDED AN ERROR CORRECTION MEMORY WHICH STORES THE LOCATION AND CORRECT INFORMATION TO BE SUBSTITUTED FOR EACH BAD BIT IN THE MAIN BULK MEMORY AND WHICH MAY BE MANUFACTURED BY THE SAME TECHNOLOGY EMPLOYED TO MAKE THE MAIN BULK MEMORY. WHEN THE BULK MEMORY IS ACCESSED, THE ERROR CORRECTION MEMORY IS ACCESSED SIMULTANEOUSLY. THE OUTPUT OF THE ERROR CORRECTING MEMORY IS SCANNED FOR AN INDICATION OF ONE OR MORE BAD BITS IN THE SIMULTANEOUSLY ACCESSED BULK MEMORY WORD. IF NO INDICATION IS FOUND, THE BULK MEMORY WORD IS CORRECT AS IT STANDS, IF ONE OR MORE INDICATIONS ARE FOUND, THE LOCATION OF THE BITS IN THE BULK MEMORY WORD AND THEIR CORRESPONDING CORRECT INFORMATION BITS ARE INSERTED INTO THE ACCESSED BULK MEMORY WORD.
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公开(公告)号：US3541530A
公开(公告)日：1970-11-17
申请号：US3541530D
申请日：1968-01-15
Applicant: IBM
Inventor： SPAMPINATO DOMINIC P , TERMAN LEWIS M
IPC: G11C11/402 , G11C11/40 , H03K3/286
CPC classification number: G11C11/4023
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公开(公告)号：US3609414A
公开(公告)日：1971-09-28
申请号：US3609414D
申请日：1968-08-20
Applicant: IBM
Inventor： PLESHKO PETER , TERMAN LEWIS M
CPC classification number: H03K17/145 , G05F3/205 , H01L27/0218 , H01L27/0738 , H01L27/088 , H03F1/301 , H03F3/345
Abstract: Apparatus is disclosed which permits the adjustment and stabilization of field effect transistor threshold voltages so that the variation in threshold voltages due to fabrication nonuniformities are reduced to a minimum. This is accomplished by utilizing one of a plurality of field effect devices on a semiconductor chip as a sensor to detect changes in the characteristics of the devices, from whatever cause. A feedback circuit provides a signal which adjusts the voltage applied to the semiconductor chip or substrate and returns the threshold voltage to some nominal value. Several circuit arrangements are shown which accomplish the desired result. A plurality of chips each having a sensor and associated feedback circuitry is also disclosed indicating the environment in which the concept of the present invention is used most advantageously.
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公开(公告)号：US3588528A
公开(公告)日：1971-06-28
申请号：US3588528D
申请日：1969-06-30
Applicant: IBM
Inventor： TERMAN LEWIS M
CPC classification number: G11C19/184
Abstract: A FOUR PHASE DIODE-FIELD-EFFECT EFFECT TRANSISTOR SHIFT REGISTER STAGE IS DISCLOSED. EACH REGISTER STAGE INCLUDES TWO IDENTICAL CIRCUITS EACH COMPRISING TWO DIODES AND A FIELD-EFFECT TRANSISTOR. EACH CIRCUIT CONTAINS A NODE WHICH IS CONNECTED TO THE GATE OF THE FIELD EFFECT TRANSISTOR OF A SUCCEEDING CIRCUIT OR TO THE FIRST CIRCUIT OF A SIMILAR SHAFT REGISTER STAGE. PULSED VOLTAGE SOURCE $1 AND $2 ARE SERIALLY DISPOSED IN ONE OF THE CIRCUITS AND PULSED VOLTAGE SOURCE $3 AND $4 ARE SERIALLY DISPOSED IN THE OTHER OF THE CIRCUITS OF EACH SHIFT REGISTER STAGE. DEPENDING ON WHETHER THE FIELD EFFECT TRANSISTORS ARE N-CHANNEL OR P-CHANNEL, PULSED VOLTAGES OF THE
PROPER POLARITY ARE APPLIED IN SEQUENCE TO APPLY A VOLTAGE TO THE NODE OF EACH CIRCUIT IN TURN. IF THE FET OF THE FIRST CIRCUIT OF A STAGE IS CONDITIONED BY PLACING INFORMATION ON ITS GATE, AND $1 AND $2 PULSES ARE APPLIED TO THE CIRCUIT IN SEQUENCE, THE GATE CAPACITANCE OF THE FET OF THE SUCCEEDING CIRCUIT IS CONDITIONED, IN RESPONSE THERETO. UPON APPLICATION OF THE $3 AND $4 PULSES TO THE SUCCEEDING CIRCUIT, THE INFORMATION PULSE ON THE GATE CAPACITANCE OF THE FIELD-EFFECT TRANSISTOR OF THE SUCCEEDING CIRCUIT IS TRANSFERRED IN INVERTED FORM TO ITS OUTPUT.-
公开(公告)号：DE69217748D1
公开(公告)日：1997-04-10
申请号：DE69217748
申请日：1992-06-25
Applicant: IBM
Inventor： DHONG SANG H , TERMAN LEWIS M
IPC: G11C11/409 , G11C11/4091
Abstract: A sensing circuit for a dynamic random access memory structure is disclosed having first and second bit lines (22A, 22B), one of the bit lines being a reference bit line which is held at a precharge voltage when a sense amplifier (40) in the sensing circuit is latched. The sense amplifier (40) includes first and second nodes (44, 42) and first, second, third and fourth transistor devices, the first and second transistor devices form an N-device cross-coupled pair (43) and the third and fourth transistor devices form a P-device cross-coupled pair (41). The first node (44) is connected to the first bit line (22A) and to the second and fourth transistor devices, and the second node (42) is connected to the first and third transistor devices. A first isolation transistor device (10) is connected to the first bit line (22A) and a second isolation transistor device (12) is connected to the second bit line (22B). A first clock signal line (32) is connected to the first isolation transistor device (10) and a second lock signal line (34) is connected to the second isolation transistor device (12). A first equalization transistor device (20) is connected to the first bit line (22A) and a second equalization transistor device (18) is connected to the second bit line (22B), a voltage signal line having a voltage value VEQ thereon is connected to the first and second equalization transistor devices (20, 18), and a third clock signal line (24) is connected to the first equalization device (20). A fourth clock signal line (26) is connected to the second equalization transistor device (18). A fifth clock signal line (30) is connected to the first and second N-devices, a sixth clock signal line (28) is connected to the third and fourth P-devices. The first, second, third, fourth and fifth and sixth clock signal lines have clock signals thereon which occur during a time sequence for precharging the first and second nodes to a precharge voltage value VEQ.
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Patent Agency Ranking
公开(公告)号：CA1230422A
公开(公告)日：1987-12-15
申请号：CA485180
申请日：1985-06-25
Applicant: IBM
Inventor： RAJEEVAKUMAR THEKKEMADATHIL V , TERMAN LEWIS M
IPC: G11C11/407 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/18 , G11C11/409 , G11C11/41 , G11C7/00
Abstract: SELF-TIMED PRECHARGE CIRCUIT of the Invention A self-timed precharge circuit for a memory array consisting of an X-line complement means connected to the outputs of a plurality of falling edge detector means, and a precharge generator means connected to the output of the X-line complement means. Each falling edge detector means is connected to a separate wordline (WL, WL+1,...WL+N) of the system memory array. In operation, the precharge generator means is triggered with a signal on the output lead from a falling edge detector which is activated when the selected wordline (WL, WL+1,...WL+N) connected thereto resets.
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公开(公告)号：DE69217748T2
公开(公告)日：1997-09-18
申请号：DE69217748
申请日：1992-06-25
Applicant: IBM
Inventor： DHONG SANG H , TERMAN LEWIS M
IPC: G11C11/409 , G11C11/4091
Abstract: A sensing circuit for a dynamic random access memory structure is disclosed having first and second bit lines (22A, 22B), one of the bit lines being a reference bit line which is held at a precharge voltage when a sense amplifier (40) in the sensing circuit is latched. The sense amplifier (40) includes first and second nodes (44, 42) and first, second, third and fourth transistor devices, the first and second transistor devices form an N-device cross-coupled pair (43) and the third and fourth transistor devices form a P-device cross-coupled pair (41). The first node (44) is connected to the first bit line (22A) and to the second and fourth transistor devices, and the second node (42) is connected to the first and third transistor devices. A first isolation transistor device (10) is connected to the first bit line (22A) and a second isolation transistor device (12) is connected to the second bit line (22B). A first clock signal line (32) is connected to the first isolation transistor device (10) and a second lock signal line (34) is connected to the second isolation transistor device (12). A first equalization transistor device (20) is connected to the first bit line (22A) and a second equalization transistor device (18) is connected to the second bit line (22B), a voltage signal line having a voltage value VEQ thereon is connected to the first and second equalization transistor devices (20, 18), and a third clock signal line (24) is connected to the first equalization device (20). A fourth clock signal line (26) is connected to the second equalization transistor device (18). A fifth clock signal line (30) is connected to the first and second N-devices, a sixth clock signal line (28) is connected to the third and fourth P-devices. The first, second, third, fourth and fifth and sixth clock signal lines have clock signals thereon which occur during a time sequence for precharging the first and second nodes to a precharge voltage value VEQ.
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公开(公告)号：CA854866A
公开(公告)日：1970-10-27
申请号：CA854866D
Applicant: IBM
Inventor： TERMAN LEWIS M , DUDA WILLIAM L
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公开(公告)号：CA1096497A
公开(公告)日：1981-02-24
申请号：CA268020
申请日：1976-12-16
Applicant: IBM
Inventor： TERMAN LEWIS M
Abstract: DIGITAL-TO-ANALOG AND ANALOG TO-DIGITAL CONVERTER CIRCUIT Digital-to-analog and analog-to-digital converter circuit embodiments are provided employing charge-transfer-device technology, for example charge-coupled-devices (CCDs). The circuit includes a plurality such as three identical CCD storage electrode plates for forming CCD wells with interposed transfer electrode gates and input and output means such as diffusions, all disposed on or in a semiconductor substrate. Means are provided for varying the potentials applied to the at least three identical electrode plates and corresponding transfer gates and a comparator means is included for comparing the voltage under the first CCD storage electrode plate with an analog voltage level to be converted to digital representation. The three identical CCD storage electrode plates function as charge dividing, accumulating and storage means and charge is transferred or shifted between CCD wells by a sequence of steps to convert an analog signal into a corresponding digital signal or, in another embodiment, a digital signal into a corresponding analog signal.
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