公开(公告)号：CA1238717A

公开(公告)日：1988-06-28

申请号：CA502801

申请日：1986-02-26

Applicant: IBM

Inventor： CHAO HU H ,  LU NICKY C

IPC: G11C11/407 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  H03K19/096

Abstract: YO984-098 BOOST WORD-LINE CLOCK AND DECODER-DRIVER CIRCUITS IN SEMICONDUCTOR MEMORIES A CMOS boost word-line clock and decoder-driver circuit which can be used for CMOS DRAM's with substrate bias in addition to VDD supply. A boost word-line clock circuit including simple CMOS inverters are used for the word-line boost and the possible voltage overshoot, which usually occurs because of capacitor two way boost, can be completely eliminated. Also, the circuit can be triggered by a single clock. A high performance decoder circuit is provided in combination with the aforesaid CMOS boost word-line clock circuit, such decoder using NMOS pass-gate in the decoder driver and providing fast word-line boosting. The timing between the decoder and the word-line clock activation is not crucial. In order to boost the word-line below O V, a negative substrate bias is provided which avoids the junction forward-biasing-due to voltage undershoot below O V at NMOS source or drain, thus simplifying the design and speeding up the word-line clock pull-down when compared to the word-line boost clock circuit without using the substrate bias.

公开(公告)号：DE68925308T2

公开(公告)日：1996-06-13

申请号：DE68925308

申请日：1989-05-17

Applicant: IBM

Inventor： DAVARI BIJAN ,  HWANG WEI ,  LU NICKY C

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L27/08 ,  H01L21/82

公开(公告)号：DE3880750D1

公开(公告)日：1993-06-09

申请号：DE3880750

申请日：1988-05-20

Applicant: IBM

Inventor： HWANG WEI ,  LU NICKY C

IPC: H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94 ,  H01L21/82

Abstract: A semiconductor memory cell structure incorporating a vertical access transistor over a trench storage capacitor including a semiconductor wafer having a semiconductor substrate (16) and an epitaxial layer (36) disposed thereon. A relatively deep polysilicon filled trench (26) is disposed in the epitaxial layer and substrate structure, the deep trench (26) having a composite oxide/nitride insulation layer (24) over its vertical and horizontal surfaces to provide a storage capacitor insulator. A relatively shallow trench is disposed in the epitaxial layer (36) over the deep trench (26) region, the shallow trench having an oxide insulation layer (46) on its vertical and horizontal surfaces thereof. A neck structure (34) of epitaxial polysilicon material extends from the top surface of the polysilicon filled deep trench (26) to the bottom surface of the shallow trench. Impurities are disposed in the epitaxial layer (36) on either side of the shallow trench to form semiconductor device drain (40) junctions and polysilicon material (48) is disposed in the shallow trench and over the epitaxial layer (36) to form semiconductor device transfer gate and wordline regions respectively.

公开(公告)号：CA1228425A

公开(公告)日：1987-10-20

申请号：CA478628

申请日：1985-04-09

Applicant: IBM

Inventor： LU NICKY C ,  NING TAK H ,  TERMAN LEWIS M

IPC: H01L27/10 ,  G11C11/34 ,  G11C11/40 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: DYNAMIC RAM CELL WITH MOS TRENCH CAPACITOR IN CMOS This invention relates generally to Dynamic Random Access Memory (DRAM) cells and more particularly relates to a DRAM cell wherein the storage capacitor of the cell is disposed in a trench formed in a semiconductor substrate. Still more particularly, it relates to a DRAM cell wherein at least a portion of the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench capacitor forms the other electrode of the storage capacitor. The DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the substrate. The well itself is formed in a lightly doped portion of the substrate and may be n or p-type conductivity with the other portions of the cell having conductivity types appropriate for devices fabricated in the CMOS environment. The trench capacitor extends from the surface of the well through the well and lightly doped substrate portion into the heavily doped portion of the substrate. The electrode disposed in the trench is directly connected to the source/drain of the access transistor.

公开(公告)号：DE68925308D1

公开(公告)日：1996-02-15

申请号：DE68925308

申请日：1989-05-17

Applicant: IBM

Inventor： DAVARI BIJAN ,  HWANG WEI ,  LU NICKY C

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L27/08 ,  H01L21/82

公开(公告)号：DE3880750T2

公开(公告)日：1993-10-28

申请号：DE3880750

申请日：1988-05-20

Applicant: IBM

Inventor： HWANG WEI ,  LU NICKY C

IPC: H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94 ,  H01L21/82

Abstract: A semiconductor memory cell structure incorporating a vertical access transistor over a trench storage capacitor including a semiconductor wafer having a semiconductor substrate (16) and an epitaxial layer (36) disposed thereon. A relatively deep polysilicon filled trench (26) is disposed in the epitaxial layer and substrate structure, the deep trench (26) having a composite oxide/nitride insulation layer (24) over its vertical and horizontal surfaces to provide a storage capacitor insulator. A relatively shallow trench is disposed in the epitaxial layer (36) over the deep trench (26) region, the shallow trench having an oxide insulation layer (46) on its vertical and horizontal surfaces thereof. A neck structure (34) of epitaxial polysilicon material extends from the top surface of the polysilicon filled deep trench (26) to the bottom surface of the shallow trench. Impurities are disposed in the epitaxial layer (36) on either side of the shallow trench to form semiconductor device drain (40) junctions and polysilicon material (48) is disposed in the shallow trench and over the epitaxial layer (36) to form semiconductor device transfer gate and wordline regions respectively.

公开(公告)号：CA1222064A

公开(公告)日：1987-05-19

申请号：CA481724

申请日：1985-05-16

Applicant: IBM

Inventor： LU NICKY C

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: THREE-DIMENSIONAL DYNAMIC RAM CELL of the Invention This invention relates generally to Dynamic Random Access Memory (DRAM) cells and more particularly relates to a DRAM cell wherein the storage capacitor of the cell is disposed in a trench formed in a semiconductor substrate. Still more particularly it relates to a DRAM cell wherein the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench forms the electrode of the storage capacitor. The DRAM cell includes an access transistor which is disposed over and in registry with the storage capacitor. The electrode of the latter is connected directly to the source of the access transistor.