公开(公告)号：JPH10307748A

公开(公告)日：1998-11-17

申请号：JP9342298

申请日：1998-04-06

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  JOHN STEPHEN DODSON ,  JERRY DON LEWIS ,  DEREK EDWARD WILLIAMS

IPC: G06F12/00 ,  G06F13/364

Abstract: PROBLEM TO BE SOLVED: To obtain the improved method and system for controlling access to the common resource by allocating a current priority level which is decided at random as to a previous priority level of a requester and allowing a request for access to the resource in response to the current priority level of the requester. SOLUTION: The number of requests for access to the common resource which can be allowed at the same time is less than the number of requests that requesters 12, 14, 16 and 18 can generate. A resource controller 20, therefore, allows only a requester selected out of the requesters 12, 14, 16 and 18 according to the priority levels to make a request when receiving requests for access to the common resource 22 more than the number of requests that can be allowed at the same time. At this time, the resource controller 20 allocates the at least top priority to one of the requesters 12, 14, 16 and 18 on a substantially on-deterministic basis by making use of input from a pseudo- random number generator 24.

公开(公告)号：JPH10301849A

公开(公告)日：1998-11-13

申请号：JP9745798

申请日：1998-04-09

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  JOHN STEPHEN DODDSON ,  JERRY DON LEWIS

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To correctly track a sector valid at the level of a higher order without executing a useless bus operation by displaying that the sector of a cache line inside a second cache is changed upstream by the cache of a second level. SOLUTION: Three 'U' states are provided so as to indicate which sector inside the cache line is changed, or whether enable cache write through operation is executed to the cache line. Then, a first value is loaded into a cache line block inside the cache of the first level of a processor and the sector of the cache line inside the cache of the second level. Then, the value inside the cache line block inside the cache of the first level is changed. Then, it is displayed by the cache of the second level that the cache line inside the cache of the second level is changed upstream.

公开(公告)号：JPH10326226A

公开(公告)日：1998-12-08

申请号：JP10281398

申请日：1998-04-14

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  DODSON JOHN STEVEN

IPC: G06F12/08 ,  G06F12/12

Abstract: PROBLEM TO BE SOLVED: To control a cache including a plurality of entries by substituting one alternative entry, which is different from an entry for substitution discriminated among entries, in response to a contention between a 1st and a 2nd caching operation request. SOLUTION: 1st and 2nd caching operation requests are received. Then one of entries in the cache is discriminated for substitution in response to the reception of the 2nd caching operation request. Here, if there is a contention between the 1st and 2nd caching operation requests, one alternative entry which is different from the entry for substitution is substituted in response. For example, a multiprocessor type data system 10 is equipped with more than one processors 12. Each processor 12 includes an on-board type level-1(L1) cache 14 which operates as a local storage device for instructions and data.

公开(公告)号：JPH10307756A

公开(公告)日：1998-11-17

申请号：JP7887398

申请日：1998-03-26

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  LEO JAMES CLARK ,  JOHN STEPHEN DODDSON ,  JERRY DON LEWIS

IPC: G06F12/08 ,  G06F12/12

Abstract: PROBLEM TO BE SOLVED: To obtain an improved cache for the processor in a computer system by introducing randomness of certain level selectively in substitution algorithm and excluding a cache block according to the substitution algorithm. SOLUTION: The cache 60 includes a cache entry array 62 having various values, a cache directory 64 for tracing entries, and a substitution controller 66 which uses LRU algorithm altered selectively with a random number. Then when slight randomness is desirable, small randomness is introduced in a 2nd deformation example 70 and the substitution algorithm is altered. In a final modification example 74, no LRU bit is used and a block excluded in an 8- member class is completely selected with three random bits. Therefore, this is applicable to a single-processor computer system and a multiprocessor computer system.

公开(公告)号：JPH10301907A

公开(公告)日：1998-11-13

申请号：JP9777198

申请日：1998-04-09

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  JOHN STEPHEN DODDSON ,  JERRY DON LEWIS ,  DEREK EDWARD WILLIAMS

IPC: G06F15/16 ,  G06F13/364 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To minimize waiting time and to suppress live lock by allocating highest present priority among plural present priorities to the priority before plural requesters at random and approving a selected request in response to access to the shared resources of the plural requesters. SOLUTION: A resource controller 20 controls the access by the requesters 12-18 to the shared resource 22. In this case, a performance monitor 54 monitors and counts selected events inside a data processing system 10 including the request from the requesters 12-18. Then, at the time of receiving the requests more than the access to the shared resource 22 simultaneously approvable by the resource controller 20, the resource controller 20 utilizes input from a pseudo random generator 24, allocates the highest priority to one of the requesters 12-18 by a practically non-critical method and approves the request of only the selected one of the requesters 12-18 corresponding to the priority.

公开(公告)号：JPH10301851A

公开(公告)日：1998-11-13

申请号：JP9600798

申请日：1998-04-08

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  JOHN STEPHEN DODDSON ,  JERRY DON LEWIS

IPC: G06F12/08 ,  G06F9/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/42

Abstract: PROBLEM TO BE SOLVED: To provide improved method and system for sharing cache memory data by reading requested data from a cache memory inside a processor before composite responses are returned from all the processors inside a data processing system to the processor. SOLUTION: The data processing system is provided with at least one CPU 11a-11n and provided with at least one each of primary cache 12a 12n and secondary cache 13a-13n and one high performance I/O device 16a-16n. In response to the request of the data by the high performance I/O device 16a-16n inside the data processing system, an intervention response is issued from the CPU 11a-11n provided with the requested data inside the data processing system. Then, the requested data are read from the secondary cache 13a-13n inside the CPU 11a-11n before the composite response is returned from all the CPUs 11a-11n inside the data processing system to the CPU 11a-11n.