公开(公告)号：JPH10254773A

公开(公告)日：1998-09-25

申请号：JP3483598

申请日：1998-02-17

Applicant: IBM

Inventor： RAVI KUMER ARIMIRRI ,  JOHN STEPHEN DODSON ,  JERRY DON LEWIS ,  DEREK EDWARD WILLIAMS

IPC: G06F9/52 ,  G06F12/08 ,  G06F15/16 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To provide a method for loading/reserving instruction by marking a highest-order cache as a reserved one, sending reserving bus operation from the highest-order cache to a cache at a second level and casting out this value from the highest-order cache after sending. SOLUTION: When a processor first accesses a value to read by the loading and reserving instruction, the value is placed at all the cache levels to the highest-order level cache (30). A corresponding block in the cache is marked as a reserved one (32). After then, the processor executes another instruction (34). When the value is expelled from the highest-order level cache (36), reserving bus operation is sent to a level just under it (38) but sent to only the level just under it. After receiving bus operation is sent to a next low-order level cache, a block is assign-released from the cache at the highest-order level (40).

公开(公告)号：JPH10307748A

公开(公告)日：1998-11-17

申请号：JP9342298

申请日：1998-04-06

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  JOHN STEPHEN DODSON ,  JERRY DON LEWIS ,  DEREK EDWARD WILLIAMS

IPC: G06F12/00 ,  G06F13/364

Abstract: PROBLEM TO BE SOLVED: To obtain the improved method and system for controlling access to the common resource by allocating a current priority level which is decided at random as to a previous priority level of a requester and allowing a request for access to the resource in response to the current priority level of the requester. SOLUTION: The number of requests for access to the common resource which can be allowed at the same time is less than the number of requests that requesters 12, 14, 16 and 18 can generate. A resource controller 20, therefore, allows only a requester selected out of the requesters 12, 14, 16 and 18 according to the priority levels to make a request when receiving requests for access to the common resource 22 more than the number of requests that can be allowed at the same time. At this time, the resource controller 20 allocates the at least top priority to one of the requesters 12, 14, 16 and 18 on a substantially on-deterministic basis by making use of input from a pseudo- random number generator 24.

公开(公告)号：JPH10260899A

公开(公告)日：1998-09-29

申请号：JP5108698

申请日：1998-03-03

Applicant: IBM

Inventor： RAVI KUMER ARIMIRRI ,  JOHN STEPHEN DODSON ,  JERRY DON LEWIS

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To provide an improved mechanism for maintaining the cache coherency in a data processing system, by forcedly setting corrected data in an independent data cache to be at a lower order cache hierarchy level. SOLUTION: Processors 102 and 104 contain independent level one instruction caches and level one data caches in the respective processors. The processor 102 contains the instruction cache 106 and the data cache 108 and the processor 104 contains the instruction cache 110 and the data cache 112. Thus, cache coherency is guaranteed in the data processing system using cache hierarchy having the independent instruction caches 106 and 110 and the data caches 108 and 112 in at least one level. Namely, the independent instruction caches 106 and 110 and the data caches 108 and 112 are efficiently made coherent.