公开(公告)号：AT291758T

公开(公告)日：2005-04-15

申请号：AT01931886

申请日：2001-05-18

Applicant: IBM

Inventor： RAWSON FREEMAN LEIGH III

IPC: H04J3/06 ,  G06F15/16

Abstract: A system and method for synchronizing a set of nodes connected to a central switch in a multi-node data processing system, such as a NUMA data processing system, are disclosed. Initially, time base register values are retrieved from each of the set of nodes. A common time base register value is then determined based upon the time base register values received from the nodes. The common time base register value that is determined is then broadcast to each of the nodes. Prior to reading the time base register values, packet traffic among the set of nodes may be halted by broadcasting a halt traffic packet to each of the nodes. In this embodiment, normal packet traffic may be resumed after synchronization by broadcasting a resume traffic packet to each of the nodes. The time base register values may be read by issuing a special purpose interrupt from a node adapter to one of the node processors in response to the adapter receiving a read time base packet from the switch. The common time base register value may be determined by selecting the maximum of the time base register values read from each of the set of nodes and adjusting the maximum time base register value by an adjustment factor, such as the time required for a packet to travel from the central switch to a node processor plus the time required for a packet to travel from a node processor to the central switch. The synchronization process may be repeated periodically such as by initiating a synchronization each time a decrementing register of the central switch reaches zero.

公开(公告)号：GB2497835B

公开(公告)日：2014-01-01

申请号：GB201219071

申请日：2012-10-24

Applicant: IBM

Inventor： RAJAMANI KARTHICK ,  CARTER JOHN BRUCE ,  HUANG WEI ,  SUDAN KSHITIJ ,  RAWSON FREEMAN LEIGH III

IPC: G06F1/32

Abstract: A system, and computer program product for increasing a capacity of a memory are provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier including a first subset of ranks from the set of ranks in the memory, and the hot tier including a second subset of ranks from the set of ranks in the memory. A determination is made whether a page to which a memory access request is directed is located in the cold tier in the memory. In response to the page being located in the cold tier of the memory, the processing of the memory access request is throttled by processing the memory access request with a delay.

公开(公告)号：GB2494341B

公开(公告)日：2013-08-07

申请号：GB201222339

申请日：2011-05-23

Applicant: IBM

Inventor： ELNOZAHY ELMOOTAZBELLAH NABIL ,  HANSON HEATHER LYNN ,  RAWSON FREEMAN LEIGH III ,  ALLEN-WARE MALCOLM SCOTT

IPC: G06F1/32 ,  G06F9/48 ,  G06F9/50

Abstract: A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.

公开(公告)号：GB2488631A

公开(公告)日：2012-09-05

申请号：GB201201713

申请日：2012-02-01

Applicant: IBM

Inventor： RAWSON FREEMAN LEIGH III ,  BREY THOMAS ,  DHOLAKIA AJAY ,  ALLEN-WARE MALCOLM SCOTT ,  GEISSLER ANDREW ,  BIESWANGER ANDREAS ,  MCCREARY HYE-YOUNG

IPC: G06F1/32

Abstract: A method and computer program product for dynamic power and performance calibration of a data processing system comprises executing a program 804 responsive to detecting an event 802, the program configured to generate data 806 indicative of the systemâ s power-performance characteristics or metrics which are measured under varying conditions of operation. The set of data is used to determine a performance or power limit on an operation of the system under present operation conditions, and a parameter of the system is calibrated 810 to operate the system within the performance limit. The program may cause the system to exhibit a behaviour approximating behaviour evident from initial power-performance data. A power-performance model may be created 808 using the set of data. Calibrating the system may include adjusting a planned workload on the system. The event may be a power-on self test event, a workload configuration event or a system configuration event.

公开(公告)号：MY119546A

公开(公告)日：2005-06-30

申请号：MYPI20005559

申请日：2000-11-28

Applicant: IBM

Inventor： RAWSON FREEMAN LEIGH III

IPC: G06F1/12

Abstract: IN A MULTI-NODE NON-UNIFORM MEMORY ACCESS (NUMA) MULTI-PROCESSOR SYSTEM, A DESIGNATED NODE SYNCHRONIZATION PROCESSOR ON EACH NODE, IS SYNCHRONIZED. INDIVIDUAL NODES ACCOMPLISH INTERNAL SYNCHRONIZATION OF THE OTHER PROCESSOR ON EACH NODE UTILIZING WELL KNOWN TECHNIQUES.THUS IT IS SUFFICIENT TO SYNCHORNIZE ONE PROCESSOR ON EACH NODE. NODE ZERO, A DESIGNATED SYSTEM NODE THAT ACTS AS A SYNCHRONIZATION MANAGER, ESTIMATES THE ITEM IT TAKES TO TRANSMIT INFORMATION IN PACKET FORM TO A PARTICULAR,REMOTE NODE IN THE SYSTEM. AS A RESULT A TIME VALUE IS TRANSMITTED FROM THE REMOTE NODE TO NODE ZERO. NODE ZERO PROJECTS THE CURRENT TIME ON THE REMOTE NODE, BASED ON THE TRANSMISSION TIME ESTIMATE AND COMPARES THAT WITH ITS OWN TIME AND EITHER UPDATES ITS OWN CLOCK TO CATCH UP WITH A LEADING REMOTE NODE OR SENDS A NEW TIME VALUE TO THE OTHER NODE, REQUIRING THE REMOTE NODE TO ADVANCE ITS TIME TO CATCH UP WITH THAT ON NODE ZERO. CODE ON THE REMAINING NODES IS MOSTLY PASSIVE, RESPONDING TO PACKETS COMING FROM NODE ZERO AND SETTING THE TIME BASE VALUE WHEN REQUESTED.MONOTONICITY OF THE TIME BASES IS MAINTANED BY ALWAYS ADVANCING THE EARLIEST OF THE TWO TIME BASES SO AS TO CATCH UP WITH THE LATER ONE.