公开(公告)号：WO2011147777A3

公开(公告)日：2012-11-22

申请号：PCT/EP2011058365

申请日：2011-05-23

Applicant: IBM ,  IBM UK ,  ELNOZAHY ELMOOTAZBELLAH NABIL ,  HANSON HEATHER LYNN ,  RAWSON III FREEMAN LEIGH ,  ALLEN-WARE MALCOLM SCOTT

Inventor： ELNOZAHY ELMOOTAZBELLAH NABIL ,  HANSON HEATHER LYNN ,  RAWSON III FREEMAN LEIGH ,  ALLEN-WARE MALCOLM SCOTT

IPC: G06F9/48 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F9/4893 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/5044 ,  G06F9/5094 ,  G06F2209/508 ,  Y02D10/126 ,  Y02D10/22 ,  Y02D10/24

Abstract: A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.

Abstract translation: 提供了一种调度应用程序任务的机制。 调度器接收标识期望频率和期望的最大数量的竞争硬件线程的任务。 调度器确定用户偏好是指性能的最大化还是能量消耗的最小化。 响应于指定性能的用户偏好，调度器确定在多个处理器核心中是否存在可用的空闲处理器核心。 响应于没有空闲处理器可用，调度器识别具有最小负载系数的处理器核心的子集。 从处理器核心的子集中，调度器确定是否存在与任务的期望参数匹配的至少一个处理器核心。 响应于至少一个与任务的期望参数匹配的处理器核心，调度器将该任务分配给与期望参数匹配的至少一个处理器核心中的一个。

公开(公告)号：DE112012003212T5

公开(公告)日：2014-07-03

申请号：DE112012003212

申请日：2012-05-14

Applicant: IBM

Inventor： ALLEN-WARE MALCOLM SCOTT ,  CARTER JOHN BRUCE ,  HANSON HEATHER LYNN ,  HUANG WEI ,  RAJAMANI KARTHICK ,  LEFURGY CHARLES ROBERT

IPC: H03K7/00

Abstract: Ein Verfahren, ein System und ein Computerprogrammprodukt zum Verbessern der Leistungsfähigkeit einer digitalen Schaltung werden in den veranschaulichenden Ausführungsformen bereitgestellt. Eine tatsächliche Arbeitsfrequenz der digitalen Schaltung wird mithilfe einer Regelschleife in der digitalen Schaltung angepasst, wobei das Anpassen der tatsächlichen Frequenz als Reaktion auf eine Änderung bei einem Betriebszustand der digitalen Schaltung erfolgt. Eine Messung eines durch die digitale Schaltung aufgenommenen Stroms wird von einem Spannungsregler empfangen, welcher der digitalen Schaltung elektrische Leistung bereitstellt. Ein Überstrom-Zielstromwert wird empfangen. Eine Spannungsabgabe vom Spannungsregler an die digitale Schaltung wird so angepasst, dass der durch die digitale Schaltung aufgenommene Strom den Überstrom-Zielstromwert nicht überschreitet.

公开(公告)号：DE112011101086T5

公开(公告)日：2013-04-11

申请号：DE112011101086

申请日：2011-05-23

Applicant: IBM

Inventor： RAWSON III FREEMAN LEIGH ,  ALLEN-WARE MALCOLM SCOTT ,  ELNOZAHY ELMOOTAZBELLAH NABIL ,  HANSON HEATHER LYNN

IPC: G06F9/50

Abstract: Ein Mechanismus zum Planen von Anwendungsaufgaben wird bereitgestellt. Ein Scheduler empfängt eine Aufgabe, die eine Sollfrequenz und eine maximale Sollzahl von konkurrierenden Hardware-Threads identifiziert. Der Scheduler ermittelt, ob eine Benutzereinstellung entweder eine Maximierung der Leistung oder eine Verringerung des Energieverbrauchs festlegt. Als Reaktion auf die Benutzereinstellung, die die Leistung festlegt, ermittelt der Scheduler, ob ein inaktiver Prozessorkern in einer Vielzahl von Prozessorkernen zur Verfügung steht. Als Reaktion darauf, dass kein inaktiver Prozessor zur Verfügung steht, identifiziert der Scheduler eine Teilmenge von Prozessorkernen, die einen niedrigsten Lastkoeffizienten aufweisen. Der Scheduler ermittelt anhand der Teilmenge von Prozessorkernen, ob mindestens ein Prozessorkern vorhanden ist, der mit den Sollparametern der Aufgabe übereinstimmt. Als Reaktion darauf, dass mindestens ein Prozessorkern mit den Sollparametern der Aufgabe übereinstimmt, weist der Scheduler die Aufgabe einem des mindestens einen Prozessorkerns zu, der mit den Sollparametern übereinstimmt.

公开(公告)号：GB2494341A

公开(公告)日：2013-03-06

申请号：GB201222339

申请日：2011-05-23

Applicant: IBM

Inventor： ELNOZAHY ELMOOTAZBELLAH NABIL ,  HANSON HEATHER LYNN ,  RAWSON FREEMAN LEIGH III ,  ALLEN-WARE MALCOLM SCOTT

IPC: G06F1/32 ,  G06F9/48 ,  G06F9/50

Abstract: A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.

公开(公告)号：GB2494341B

公开(公告)日：2013-08-07

申请号：GB201222339

申请日：2011-05-23

Applicant: IBM

Inventor： ELNOZAHY ELMOOTAZBELLAH NABIL ,  HANSON HEATHER LYNN ,  RAWSON FREEMAN LEIGH III ,  ALLEN-WARE MALCOLM SCOTT

IPC: G06F1/32 ,  G06F9/48 ,  G06F9/50

Abstract: A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.

公开(公告)号：GB2488631A

公开(公告)日：2012-09-05

申请号：GB201201713

申请日：2012-02-01

Applicant: IBM

Inventor： RAWSON FREEMAN LEIGH III ,  BREY THOMAS ,  DHOLAKIA AJAY ,  ALLEN-WARE MALCOLM SCOTT ,  GEISSLER ANDREW ,  BIESWANGER ANDREAS ,  MCCREARY HYE-YOUNG

IPC: G06F1/32

Abstract: A method and computer program product for dynamic power and performance calibration of a data processing system comprises executing a program 804 responsive to detecting an event 802, the program configured to generate data 806 indicative of the systemâ s power-performance characteristics or metrics which are measured under varying conditions of operation. The set of data is used to determine a performance or power limit on an operation of the system under present operation conditions, and a parameter of the system is calibrated 810 to operate the system within the performance limit. The program may cause the system to exhibit a behaviour approximating behaviour evident from initial power-performance data. A power-performance model may be created 808 using the set of data. Calibrating the system may include adjusting a planned workload on the system. The event may be a power-on self test event, a workload configuration event or a system configuration event.

公开(公告)号：GB2509658B

公开(公告)日：2015-12-30

申请号：GB201407236

申请日：2012-11-01

Applicant: IBM

Inventor： ALLEN-WARE MALCOLM SCOTT ,  CARTER JOHN BRUCE ,  HUANG WEI ,  LEFURGY CHARLES R ,  SILVA GUILLERMO J

IPC: G06F1/20 ,  G05D23/19 ,  G06F1/32

Abstract: A mechanism is provided for minimizing system power in the data processing system with fast convergence. A current aggregate system power value is determined using a current thermal threshold value. For each potential thermal threshold value in a set of potential thermal threshold values, a determination is made as to whether there is a potential thermal threshold value that results in a potential aggregate system power value that is lower than the current aggregate system power value. Responsive to identifying an optimal potential thermal threshold value from the set of potential thermal threshold values that results in minimum aggregate system power value that is lower than the current aggregate system power value, the optimal potential thermal threshold value is set as a new thermal threshold value.

公开(公告)号：GB2506083B

公开(公告)日：2015-01-21

申请号：GB201400568

申请日：2012-05-14

Applicant: IBM

Inventor： ALLEN-WARE MALCOLM SCOTT ,  LEFURGY CHARLES ROBERT ,  HANSON HEATHER LYNN ,  CARTER JOHN BRUCE ,  HUANG WEI ,  RAJAMANI KARTHICK

IPC: G06F1/32

Abstract: A method for improving the performance of a digital circuit is provided in the illustrative embodiments. A real frequency of operation of the digital circuit is adjusted using a control loop in the digital circuit, the adjusting the real frequency being responsive to a change in an operating condition of the digital circuit. A measurement of a current drawn by the digital circuit is received from a voltage regulator supplying electrical power to the digital circuit. An over-current target current value is received. A voltage output from the voltage regulator to the digital circuit is adjusted such that the current drawn by the digital circuit does not exceed the over-current target current value.

公开(公告)号：GB2506083A

公开(公告)日：2014-03-19

申请号：GB201400568

申请日：2012-05-14

Applicant: IBM

Inventor： ALLEN-WARE MALCOLM SCOTT ,  LEFURGY CHARLES ROBERT ,  HANSON HEATHER LYNN ,  CARTER JOHN BRUCE ,  HUANG WEI ,  RAJAMANI KARTHICK

IPC: G06F1/32

Abstract: A method, system, and computer program product for improving the performance of a digital circuit are provided in the illustrative embodiments. A real frequency of operation of the digital circuit is adjusted using a control loop in the digital circuit, the adjusting the real frequency being responsive to a change in an operating condition of the digital circuit. A measurement of a current drawn by the digital circuit is received from a voltage regulator supplying electrical power to the digital circuit. An over-current target current value is received. A voltage output from the voltage regulator to the digital circuit is adjusted such that the current drawn by the digital circuit does not exceed the over-current target current value.

公开(公告)号：GB2515223B

公开(公告)日：2015-04-15

申请号：GB201417152

申请日：2013-03-27

Applicant: IBM

Inventor： ALLEN-WARE MALCOLM SCOTT ,  DRAKE ALAN JAMES ,  HUANG WEI ,  FLOYD MICHAEL STEPHEN ,  WEN HUAJUN

IPC: G06F1/32

Abstract: A mechanism is provided for minimizing power consumption for operation of a fixed-frequency processing unit. A number of timeslots are counted in a time window where throttling is engaged to the fixed-frequency processing unit. The number of timeslots where throttling is engaged is divided by a total number of timeslots within the time window, thereby producing a performance loss (PLOSS) value. A determination is made as to whether determining whether the (PLOSS) value associated with the fixed-frequency processing unit is greater than an allowed performance loss (APLOSS) value. Responsive to the PLOSS value being less than or equal to the APLOSS value, a decrease in voltage supplied to the fixed-frequency processing unit is initiated.