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Patent Agency Ranking
公开(公告)号：GB1213382A
公开(公告)日：1970-11-25
申请号：GB391068
申请日：1968-01-25
Applicant: IBM
Inventor： RISO VLADIMIR
IPC: G06G7/163
Abstract: 1,213,382. Electric analogue multiplying. INTERNATIONAL BUSINESS MACHINES CORP. 25 Jan., 1968 [25 Jan., 1967], No. 3910/68. Heading G4G. [Also in Division H3] Analogue multiplication circuit (Fig. 3) receives a voltage Ve over series resistance to an input of amplifier A 1 energizing the gate of field effect transistor T 1 , operating as a resistance variable with Ve in series with source load resistance R 4 ; whose drain and source are D.C. energized from supply Œ U with negative feedback from source to amplifier input; the source output V o being connected to an input of amplifier A 2 and the output of amplifier A 1 being applied to a second opposed input over variable resistance R 8 . Negative feedback is provided over R 6 and the output excites the gate of a similarly operating field effect transistor T 2 whose drain and source are energized from supply ŒV in series with variable source load resistance R 10 from which negative feedback is applied to the second input of A 2 . It is shown that the output voltage V s across R 10 is linearly proportional to Ve.V/U; R 8 , R 10 being adjustable for zero. In a modification (Fig. 6, not shown) the drain/source circuit of a field effect transistor is energized from a supply of Œ (U+V) wherein U is D.C. and V is A.C. voltage in series with a load resistance; the gate is energized from an amplifier to which an input Ve is applied over a series resistance, together with feedback of the output voltage V s across the load resistance over a low pass T network incorporating series reistance R 14 , R 15 and shunt capacitance C; it is shown that V s = KV e V. In a further modification (Fig. 4, not shown) V s -V o is negligibly small compared with e, and voltages V o , V s need not be transferred to the input of the second stage amplifier. The feedback of this amplifier and the bias of the output FET are potentiometrically controlled. In a further modification (Fig. 7, not shown) a further amplifier is inserted in the circuit of Fig. 6 (not shown) to the input of which an adjustable A.C. is applicable.
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公开(公告)号：FR95047E
公开(公告)日：1970-03-27
申请号：FR06009089
申请日：1968-03-20
Applicant: IBM FRANCE
Inventor： BURON RENE , LEVILION MARC , NUSSBAUMER HENRI , PARIS ETIENNE , RISO VLADIMIR
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公开(公告)号：FR1517048A
公开(公告)日：1968-06-24
申请号：FR06008323
申请日：1967-01-25
Applicant: IBM FRANCE
Inventor： RISO VLADIMIR
IPC: G06G7/163
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公开(公告)号：FR1478431A
公开(公告)日：1967-04-28
申请号：FR06007736
申请日：1966-02-07
Applicant: IBM FRANCE
Inventor： PECKELS JEAN-PIERRE , RISO VLADIMIR
IPC: G10L25/00
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