公开(公告)号：FR2298137A1

公开(公告)日：1976-08-13

申请号：FR7501855

申请日：1975-01-14

Applicant: IBM FRANCE

Inventor： DAUBY ALAIN ,  RODES DANIEL ROGER ,  RISO VLADIMIR

IPC: G06F7/508 ,  G06F7/52 ,  G06F7/523 ,  G06F7/48 ,  H03K19/34

公开(公告)号：FR2293743A1

公开(公告)日：1976-07-02

申请号：FR7441660

申请日：1974-12-03

Applicant: IBM FRANCE

Inventor： RISO VLADIMIR

IPC: G06F17/16 ,  G06F7/544 ,  H03H17/00 ,  G06F7/39

公开(公告)号：FR95047E

公开(公告)日：1970-03-27

申请号：FR06009089

申请日：1968-03-20

Applicant: IBM FRANCE

Inventor： BURON RENE ,  LEVILION MARC ,  NUSSBAUMER HENRI ,  PARIS ETIENNE ,  RISO VLADIMIR

IPC: A47F7/19 ,  G10L19/02 ,  G10L21/00 ,  H04B1/66 ,  H04B14/06 ,  G01L

公开(公告)号：DE3375611D1

公开(公告)日：1988-03-10

申请号：DE3375611

申请日：1983-03-29

Applicant: IBM ,  IBM FRANCE

Inventor： RISO VLADIMIR ,  KUHNE ROLAND

IPC: G06F13/36 ,  G06F13/42 ,  H04L25/24 ,  H04L25/52

Abstract: A number (e.g. sixteen) of processors are connected to a central control unit by a common bus having half that number of wires (D0-D7) reserved for a byte of data or control bits, one line for a parity bit and one for a control bit. In the bus interface each line (D0-D7) is associated with two flip-flops (40,41) having direct and inverted (44) inputs of a first clock signal (CLK1). When received bits are in NRZ code with duration equal to half the clock period, output OR gates (47) reproduce resynchronised input bits. Processors divided into two equal gps. request access during one or other phase of a second clock signal. The state of access requests is indicated by memory flip-flops (48,49) when the bus is free.

公开(公告)号：FR1517048A

公开(公告)日：1968-06-24

申请号：FR06008323

申请日：1967-01-25

Applicant: IBM FRANCE

Inventor： RISO VLADIMIR

IPC: G06G7/163

公开(公告)号：FR1478431A

公开(公告)日：1967-04-28

申请号：FR06007736

申请日：1966-02-07

Applicant: IBM FRANCE

Inventor： PECKELS JEAN-PIERRE ,  RISO VLADIMIR

IPC: G10L25/00