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    11.
    发明专利
    未知

    公开(公告)号：DE3586635T2

    公开(公告)日：1993-04-08

    申请号：DE3586635

    申请日：1985-02-28

    Applicant: IBM

    Inventor： POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

    IPC: G06F12/08

    Abstract: An efficient prefetching mechanism is disclosed for a system comprising a cache. In addition to the normal cache directory (11), a two-level shadow directory (13, 15) is provided. When an information block is accessed, a parent identifer (P) derived from the block address is stored in the top level (13) of the shadow directory. The address of a subsequently accessed block (Q) is stored in the second level (15) of the shadow directory, in a position associated with the first-level position of the respective parent identifier. … With each access to an information block, a check is made whether the respective parent identifier (P) is already stored in the first level of the shadow directory. If it is found, then the descendant address (Q) from the associated second-level position is used to prefetch an information block to the cache if it is not already resident therein. This mechanism avoids with high probability the occurence of cache misses.

    12.
    发明专利
    未知

    公开(公告)号：DE3682700D1

    公开(公告)日：1992-01-16

    申请号：DE3682700

    申请日：1986-03-14

    Applicant: IBM

    Inventor： POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  ROSENFELD PHILIP LEWIS ,  SPARACIO FRANK JOHN

    IPC: G06F9/38

    Abstract: A branch history table (BHT) is substantially improved by dividing it into two parts: an active area, and a backup area. The active area contains entries for a small number of branches which the processor can encounter in the near future and the backup area contains all other branch entries. Means are provided to bring entries from the backup area into the active area ahead of when the processor will use those entries. When entries are no longer needed they are removed from the active area and put into the backup area if not already there. New entries for the near future are brought in, so that the active area, though small, will almost always contain the branch information needed by the processor. The small size of the active area allows it to be fast and to be optimally located in the processor layout. The backup area can be located outside the critical part of the layout and can therefore be made larger than would be practicable for a standard BHT.

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