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    4.
    发明专利
    未知

    公开(公告)号：DE3750306T2

    公开(公告)日：1995-03-09

    申请号：DE3750306

    申请日：1987-04-24

    Applicant: IBM

    Inventor： POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

    IPC: G06F9/38

    Abstract: A method and apparatus for controlling access to its general purpose registers (GPR) by a high end machine configuration including a plurality of execution units within a single central processing unit (CPU). The invention allows up to "N" execution units to be concurrently executing up to "N" instructions using the same general purpose register (GPR) sequentially or different general purpose registers (GPR) concurrently as either SINK or SOURCE while at the same time preserving the logical integrity of the data supplied to the execution units. The use of the invention allows a higher degree of parallelism in the execution of the instructions than would otherwise be possible if only sequential operations were performed. A series of special purpose tags are associated with each general purpose register (GPR) and execute unit. These tags are used together with control circuitry both within the general purpose registers (GPR), within the individual execute units and within the instruction decode unit, which permit the multiple use of the registers to be accomplished while maintaining the requisite logical integrity.

    6.
    发明专利
    未知

    公开(公告)号：DE3586635D1

    公开(公告)日：1992-10-22

    申请号：DE3586635

    申请日：1985-02-28

    Applicant: IBM

    Inventor： POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

    IPC: G06F12/08

    Abstract: An efficient prefetching mechanism is disclosed for a system comprising a cache. In addition to the normal cache directory (11), a two-level shadow directory (13, 15) is provided. When an information block is accessed, a parent identifer (P) derived from the block address is stored in the top level (13) of the shadow directory. The address of a subsequently accessed block (Q) is stored in the second level (15) of the shadow directory, in a position associated with the first-level position of the respective parent identifier. … With each access to an information block, a check is made whether the respective parent identifier (P) is already stored in the first level of the shadow directory. If it is found, then the descendant address (Q) from the associated second-level position is used to prefetch an information block to the cache if it is not already resident therein. This mechanism avoids with high probability the occurence of cache misses.

    8.
    发明专利
    未知

    公开(公告)号：DE3750306D1

    公开(公告)日：1994-09-08

    申请号：DE3750306

    申请日：1987-04-24

    Applicant: IBM

    Inventor： POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

    IPC: G06F9/38

    Abstract: A method and apparatus for controlling access to its general purpose registers (GPR) by a high end machine configuration including a plurality of execution units within a single central processing unit (CPU). The invention allows up to "N" execution units to be concurrently executing up to "N" instructions using the same general purpose register (GPR) sequentially or different general purpose registers (GPR) concurrently as either SINK or SOURCE while at the same time preserving the logical integrity of the data supplied to the execution units. The use of the invention allows a higher degree of parallelism in the execution of the instructions than would otherwise be possible if only sequential operations were performed. A series of special purpose tags are associated with each general purpose register (GPR) and execute unit. These tags are used together with control circuitry both within the general purpose registers (GPR), within the individual execute units and within the instruction decode unit, which permit the multiple use of the registers to be accomplished while maintaining the requisite logical integrity.

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