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    METHOD AND DEVICE FOR EXECUTING INSTRUCTION SEQUENCE
    2.
    发明专利
    METHOD AND DEVICE FOR EXECUTING INSTRUCTION SEQUENCE 失效

    公开(公告)号：JPH10124317A

    公开(公告)日：1998-05-15

    申请号：JP25972997

    申请日：1997-09-25

    Applicant: IBM

    Inventor： RECHTSCHAFFEN RUDOLPH NATHAN ,  KATATSUMURI EKANAHAMU

    IPC: G06F9/38 ,  G06F9/45 ,  G06F15/80 ,  G06F15/16

    Abstract: PROBLEM TO BE SOLVED: To attain efficient parallel execution by asynchronously executing substitutive encoding by plural execution devices in parallel and interfacing plural devices through a common register file. SOLUTION: Each processing element 100 can decode an instruction by the use of an instruction decoder/schedular 500, access the common register file 160 through a bus 110, generate an address for a storage operand, and access a register operand. The operand accessed by the instruction is sent to an execution device 130 in the processing element, which executes operation specified by the instruction and stores its execution result in a renamed register. Respective processing elements 100 are connected to storage hierarchy 140 through a bus 135 and the hierarchy 140 supplies a data operand in fetching operation and receives a storing operand in storing operation.

    5.
    发明专利
    未知

    公开(公告)号：DE3750306T2

    公开(公告)日：1995-03-09

    申请号：DE3750306

    申请日：1987-04-24

    Applicant: IBM

    Inventor： POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

    IPC: G06F9/38

    Abstract: A method and apparatus for controlling access to its general purpose registers (GPR) by a high end machine configuration including a plurality of execution units within a single central processing unit (CPU). The invention allows up to "N" execution units to be concurrently executing up to "N" instructions using the same general purpose register (GPR) sequentially or different general purpose registers (GPR) concurrently as either SINK or SOURCE while at the same time preserving the logical integrity of the data supplied to the execution units. The use of the invention allows a higher degree of parallelism in the execution of the instructions than would otherwise be possible if only sequential operations were performed. A series of special purpose tags are associated with each general purpose register (GPR) and execute unit. These tags are used together with control circuitry both within the general purpose registers (GPR), within the individual execute units and within the instruction decode unit, which permit the multiple use of the registers to be accomplished while maintaining the requisite logical integrity.

    Parallel processing system
    6.
    发明专利
    Parallel processing system 未知

    公开(公告)号：GB2318660A

    公开(公告)日：1998-04-29

    申请号：GB9719580

    申请日：1997-09-16

    Applicant: IBM

    Inventor： RECHTSCHAFFEN RUDOLPH NATHAN ,  EKANADHAM KATTAMURI

    IPC: G06F9/38 ,  G06F9/45 ,  G06F15/80 ,  G06F9/44

    Abstract: A self-parallelising computer system is described in which a single execution sequence of instructions is partitioned at run-time into a set of instruction subsequences, each instruction subsequence being executed on a different one of a set of separate processing elements 100 that share a common register file 160. The processing elements rename the registers used by the instructions that modify registers so that when the instructions are executed in parallel mode the result of the executions will appear in the common set of registers accessible to all the processing elements. Each instruction within the sequential execution sequence that modifies a register gets assigned the next higher number hardware register from the common register pool. The architected register modified in this instruction is now renamed to this hardware register and so identified within a register correspondence table 180 Conceptually subsequent instructions that require this register as input will now be associated with the renamed common register and derive their input from the result of the execution of the register-modifying instruction. As such there is no need for sending and receiving obligations to resolve register set/use requirements implied by the sequential execution sequence.

    8.
    发明专利
    未知

    公开(公告)号：DE3586635T2

    公开(公告)日：1993-04-08

    申请号：DE3586635

    申请日：1985-02-28

    Applicant: IBM

    Inventor： POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

    IPC: G06F12/08

    Abstract: An efficient prefetching mechanism is disclosed for a system comprising a cache. In addition to the normal cache directory (11), a two-level shadow directory (13, 15) is provided. When an information block is accessed, a parent identifer (P) derived from the block address is stored in the top level (13) of the shadow directory. The address of a subsequently accessed block (Q) is stored in the second level (15) of the shadow directory, in a position associated with the first-level position of the respective parent identifier. … With each access to an information block, a check is made whether the respective parent identifier (P) is already stored in the first level of the shadow directory. If it is found, then the descendant address (Q) from the associated second-level position is used to prefetch an information block to the cache if it is not already resident therein. This mechanism avoids with high probability the occurence of cache misses.

    9.
    发明专利
    未知

    公开(公告)号：DE3682700D1

    公开(公告)日：1992-01-16

    申请号：DE3682700

    申请日：1986-03-14

    Applicant: IBM

    Inventor： POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  ROSENFELD PHILIP LEWIS ,  SPARACIO FRANK JOHN

    IPC: G06F9/38

    Abstract: A branch history table (BHT) is substantially improved by dividing it into two parts: an active area, and a backup area. The active area contains entries for a small number of branches which the processor can encounter in the near future and the backup area contains all other branch entries. Means are provided to bring entries from the backup area into the active area ahead of when the processor will use those entries. When entries are no longer needed they are removed from the active area and put into the backup area if not already there. New entries for the near future are brought in, so that the active area, though small, will almost always contain the branch information needed by the processor. The small size of the active area allows it to be fast and to be optimally located in the processor layout. The backup area can be located outside the critical part of the layout and can therefore be made larger than would be practicable for a standard BHT.

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