公开(公告)号：DE69425377T2

公开(公告)日：2001-02-15

申请号：DE69425377

申请日：1994-11-29

Applicant: IBM

Inventor： STAIGER DIETER E

IPC: G06F9/32 ,  G06F9/22 ,  G06F9/26

Abstract: Described is a processing unit (100) with a processor (110) for processing an operation code and a method for processing the operation code in the processing unit (100). The processor (110) comprises an operation code control unit (200) for receiving and processing the operation code in a boolean circuit (230) and generating a logical result thereof, and a next address control unit (210) comprising a multiplexing unit (250) with a plurality of input lines (A-D) selectable by the multiplexing unit (250) by means of the logical result of the boolean circuit (230). The processor (110) is triggerable by a trigger signal (CLOCK) and each operation code is processable by the processor (110) between successive trigger signals (CLOCK). When the trigger signal (e.g. a CLOCK signal) appears, the processor (110) according to the invention issues a signal comprising an address of the operation code to be processed to the control memory (129) and/or a user data memory (140). The operation code corresponding to that address is loaded from the control memory (120) to the processor (110) and processed therein. One result of this processing is the address of the successive operation code to be processed, which will be processed when the successive trigger signal appears. This loading and processing of operation code happens continuously in each cycle between successive trigger signals, until the end of program is reached or an interrupt signal is calling a stop routine. Each operation code is processed between successive trigger signals (or within one CLOCK cycle) allowing a predictable timing of a sequence of operation codes so that a real time condition is achievable.

公开(公告)号：AU2003303246A8

公开(公告)日：2004-07-14

申请号：AU2003303246

申请日：2003-10-31

Applicant: IBM

Inventor： STAIGER DIETER E

IPC: B60R16/02 ,  B60R25/10 ,  B60W50/00 ,  G05B19/042 ,  H04L29/08

Abstract: The present invention relates to the field of embedded processing systems and electronic control units (ECUs) and to autonomic embedded computing solutions. The present invention proposes to remove or extract the application-specific support functions and respective I/O subsystems from the main processors or controllers of the system, to include said extracted circuits into a respective number of ASIC chips or the like, and to connect them preferably via a supervising General Controller Unit (12) to a plurality of standard and low-price processors (40), which have the task to supply the ASIC and the multiple functions thereof with enough computing power.

公开(公告)号：HK1055859A1

公开(公告)日：2004-01-21

申请号：HK03107897

申请日：2003-11-03

Applicant: IBM

Inventor： STAIGER DIETER E

IPC: H04L12/56 ,  H04L12/28 ,  H04L69/14 ,  H04L

Abstract: A method and device for communication control. It is an object to provide an improved method and device which can be used with a range of standard communication facilities. A method and device are provided for controlling communication through a data network or bus. The data network or bus includes a data source and a transmission facility subdivided into a plurality of different channels. A subset of the plurality of channels is determined which the data source is allowed to seize. A data stream originating from the data source is transformed into a format permitting concurrent transmission over the subset of channels. Finally, the transformed data is transmitted concurrently over the subset of channels. The principles taught provide a method and device which allow one to utilize the provided bandwidth of a bus or network very efficiently leading to a higher statistical availability of data transport capacity.

公开(公告)号：DE10141626A1

公开(公告)日：2002-03-28

申请号：DE10141626

申请日：2001-08-24

Applicant: IBM

Inventor： STAIGER DIETER E

IPC: G06F1/32

Abstract: A DP -C processor memory (1) has a program memory (1a) with a size adapted to any processor in use. A processor is allocated registers (1b) with system start-up conditions to be loaded as the system is initialised. A search look-up table for forecasts (1c) has situations that might occur if a system is used in machinery like a motor vehicle. The processor also has a countdown forecast timer (1d) to control the time relationship of situations stored in the forecasts.

公开(公告)号：DE19703388C1

公开(公告)日：1998-07-23

申请号：DE19703388

申请日：1997-01-30

Applicant: IBM

Inventor： STAIGER DIETER E

IPC: G06F1/32

Abstract: The method involves detecting whether data entry is being conducted via an input/output unit (8). Control logic (2) induces a standby mode for the system, at least for its processor (1), when no data entry occurs over a certain period. The control logic controls the visual display screen driver (5) so that the image displayed continues to corresp. to the processor operating mode before the mode was changed.

公开(公告)号：DE10141626B4

公开(公告)日：2007-08-09

申请号：DE10141626

申请日：2001-08-24

Applicant: IBM

Inventor： STAIGER DIETER E

IPC: G06F1/32

公开(公告)号：DE60019038T2

公开(公告)日：2006-03-30

申请号：DE60019038

申请日：2000-07-12

Applicant: IBM

Inventor： EIBACH WOLFGANG ,  STAIGER DIETER E

IPC: G06F11/00 ,  B60R16/02 ,  G05B19/042

Abstract: A principle for handling system failure situations thereby maintaining minimum fault recovery time and providing high system availability is described, especially for controlling the system behavior in fault situations of Electronic Control Units used in automotive vehicles. This principle is providing unique solutions for fault analysis, fault recovery definition and system re-vitalization. It is a key attribute of the principle keeping the demand for hardware and software overhead at a minimum. The method applies graceful degradation of system functionality, allowing to achieve the implementation of cost effective systems.

公开(公告)号：DE102004047442A1

公开(公告)日：2005-05-12

申请号：DE102004047442

申请日：2004-09-28

Applicant: IBM

Inventor： STAIGER DIETER E

IPC: G06F13/00 ,  G06F13/374 ,  H04L12/28 ,  H04L69/14 ,  H04L29/04

Abstract: Switching method and apparatus for assigning a communication grant to a first processing unit in a communication network comprising a plurality of processing units, each processing unit being connected to each other processing unit of the plurality of processing units. The switching method includes steps of performing an identical arbitration procedure for a communication grant by each of the plurality of processing units, and switching at least one of the plurality of processing units according to the identical arbitration procedure.

公开(公告)号：AT292303T

公开(公告)日：2005-04-15

申请号：AT00114893

申请日：2000-07-12

Applicant: IBM

Inventor： EIBACH WOLFGANG ,  STAIGER DIETER E

IPC: G05B19/042 ,  G06F11/00 ,  B60R16/02

Abstract: A principle for handling system failure situations thereby maintaining minimum fault recovery time and providing high system availability is described, especially for controlling the system behavior in fault situations of Electronic Control Units used in automotive vehicles. This principle is providing unique solutions for fault analysis, fault recovery definition and system re-vitalization. It is a key attribute of the principle keeping the demand for hardware and software overhead at a minimum. The method applies graceful degradation of system functionality, allowing to achieve the implementation of cost effective systems.

公开(公告)号：AU2003303246A1

公开(公告)日：2004-07-14

申请号：AU2003303246

申请日：2003-10-31

Applicant: IBM

Inventor： STAIGER DIETER E

IPC: B60R16/02 ,  B60R25/10 ,  B60W50/00 ,  G05B19/042 ,  H04L29/08

Abstract: The present invention relates to the field of embedded processing systems and electronic control units (ECUs) and to autonomic embedded computing solutions. The present invention proposes to remove or extract the application-specific support functions and respective I/O subsystems from the main processors or controllers of the system, to include said extracted circuits into a respective number of ASIC chips or the like, and to connect them preferably via a supervising General Controller Unit (12) to a plurality of standard and low-price processors (40), which have the task to supply the ASIC and the multiple functions thereof with enough computing power.