公开(公告)号：BR9005496A

公开(公告)日：1991-09-17

申请号：BR9005496

申请日：1990-10-30

Applicant: IBM

Inventor： HAUSMAN KRISTEN A ,  GAUDENZI GENE JOSEPH ,  MOSLEY JOSEPH M ,  TEMPEST SUSAN LYNN

IPC: H03K3/03 ,  H03K3/282 ,  H03B5/00

公开(公告)号：BR8902376A

公开(公告)日：1990-01-16

申请号：BR8902376

申请日：1989-05-24

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD ,  GAUDENZI GENE JOSEPH ,  KRAMER KEVIN GERRARD ,  TEMPEST SUSAN LYNN

IPC: G06F11/10 ,  G06F13/38 ,  G06F13/40 ,  H03K3/288 ,  H03K19/082 ,  H03M13/00

Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes : a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.