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公开(公告)号：IN177313B
公开(公告)日：1996-12-28
申请号：IN628DE1989
申请日：1989-07-13
Applicant: IBM
Inventor： BLAND PATRICK MAURICE , DEAN MARK EDWARD , GAUDENZI GENE JOSEPH , KRAMER KEVIN GERRARD , TEMPEST SUSAN LYNN
IPC: G06F7/00
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公开(公告)号：DE3879089T2
公开(公告)日：1993-09-16
申请号：DE3879089
申请日：1988-08-16
Applicant: IBM
Inventor： GAUDENZI GENE JOSEPH , TEMPEST SUSAN LYNN
Abstract: A voltage regulator for regulating the voltage at a first node, comprising a first voltage supply; a first node; a first transistor with a control terminal connected to the first node; means for varying the VBE voltage drop of said first transistor in accordance with whether the voltage level of the first voltage supply is above or below a threshold voltage and for continuously sinking current from said first transistor; and means for varying the voltage level at the current-emitting terminal of the first transistor to counteract, in combination with the varying VBE voltage drop, the change in the voltage level of the first voltage supply.
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公开(公告)号：DE68923818T2
公开(公告)日：1996-04-18
申请号：DE68923818
申请日：1989-04-11
Applicant: IBM
Inventor： BLAND PATRICK MAURICE , KRAMER KEVIN GERRARD , DEAN MARK EDWARD , TEMPEST SUSAN LYNN , GAUDENZI GENE JOSEPH
IPC: G06F11/10 , G06F13/38 , G06F13/40 , H03K3/288 , H03K19/082 , H03K19/00 , H03K19/0175
Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes : a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.
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Patent Agency Ranking
公开(公告)号：DE3879089D1
公开(公告)日：1993-04-15
申请号：DE3879089
申请日：1988-08-16
Applicant: IBM
Inventor： GAUDENZI GENE JOSEPH , TEMPEST SUSAN LYNN
Abstract: A voltage regulator for regulating the voltage at a first node, comprising a first voltage supply; a first node; a first transistor with a control terminal connected to the first node; means for varying the VBE voltage drop of said first transistor in accordance with whether the voltage level of the first voltage supply is above or below a threshold voltage and for continuously sinking current from said first transistor; and means for varying the voltage level at the current-emitting terminal of the first transistor to counteract, in combination with the varying VBE voltage drop, the change in the voltage level of the first voltage supply.
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公开(公告)号：SG44402A1
公开(公告)日：1997-12-19
申请号：SG1996000189
申请日：1989-04-11
Applicant: IBM
Inventor： BLAND PATRICK MAURICE , DEAN MARK EDWARD , GAUDENZI GENE JOSEPH , KRAMER KEVIN GERRARD , TEMPEST SUSAN LYNN
Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes : a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.
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公开(公告)号：CA1338155C
公开(公告)日：1996-03-12
申请号：CA596778
申请日：1989-04-14
Applicant: IBM
Inventor： BLAND PATRICK MAURICE , DEAN MARK EDWARD , GAUDENZI GENE JOSEPH , KRAMER KEVIN GERRARD , TEMPEST SUSAN LYNN
Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.
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公开(公告)号：ES2075856T3
公开(公告)日：1995-10-16
申请号：ES89480053
申请日：1989-04-11
Applicant: IBM
Inventor： BLAND PATRICK MAURICE , KRAMER KEVIN GERRARD , DEAN MARK EDWARD , TEMPEST SUSAN LYNN , GAUDENZI GENE JOSEPH
IPC: G06F11/10 , G06F13/38 , G06F13/40 , H03K3/288 , H03K19/082 , H03K19/00 , H03K19/0175
Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes : a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.
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公开(公告)号：DE68923818D1
公开(公告)日：1995-09-21
申请号：DE68923818
申请日：1989-04-11
Applicant: IBM
Inventor： BLAND PATRICK MAURICE , KRAMER KEVIN GERRARD , DEAN MARK EDWARD , TEMPEST SUSAN LYNN , GAUDENZI GENE JOSEPH
IPC: G06F11/10 , G06F13/38 , G06F13/40 , H03K3/288 , H03K19/082 , H03K19/00 , H03K19/0175
Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes : a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.
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