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1.发明公开
公开(公告)号：EP0205972A1
公开(公告)日：1986-12-30
申请号：EP86107257
申请日：1986-05-28
Applicant: IBM
Inventor： FAVATA ALFRED FILADELFIO , GAUDENZI GENE JOSEPH
IPC: H03K3/286 , H03K5/00 , H03K19/003 , H03K19/0175
CPC classification number: H03K19/00353
Abstract: A digital circuit with a logical input stage (4) and an output stage (7, 8) comprises an intermediate stage (5) which operates to temporarily increase the current through the input stage (4) upon a transition from one logical level to the other. The intermediate stage (5) includes a current source (40) which is controlled by the output potential of the input stage (4) via a feedback arrangement (43) from a circuit (50) in the intermediate stage (5) controlling the output stage (7, 8).
Abstract translation: 具有逻辑输入级（4）和输出级（7,8）的数字电路包括中间级（5），该中间级（5）用于在从一个逻辑电平转换到 其他。 中间级（5）包括电流源（40），该电流源通过来自中间级（5）中的电路（50）的反馈装置（43）由输入级（4）的输出电位控制输出 阶段（7,8）。
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公开(公告)号：JPH098447A
公开(公告)日：1997-01-10
申请号：JP14470596
申请日：1996-06-06
Applicant: IBM
IPC: H01L21/60 , H01L23/485 , H05K1/14 , H05K3/34
Abstract: PROBLEM TO BE SOLVED: To manufacture an organic laminated circuit card for direct chip mounting by a method wherein a device carrier is electrically connected with a device through a solder ball having a cap, which consists of a low-melting point material which forms an eutectic alloy. SOLUTION: A solder ball 38 is fixed on a ball limiting metallized layer 48. An internal metal wiring 32 conducts the electrical connection between an IC chip 30 and a cap 41. The low-melting point metal cap 41 consists of one kind of a metal selected from a group consisting of bismuth, indium, tin or their alloy. The ball 38 consists of one kind of an alloy selected from a group consisting of a high-melting point solder and a low-melting point solder or C4. It is necessary that the material for the cap 41 is a metal which forms an eutectic alloy. After the chip 30 having the cap 41 on the ball 38 is fixed on a circuit card, the chip 41 is reflowed to form the eutective alloy and the ball 38 is bonded to a copper wiring 20.
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公开(公告)号：JPH10303059A
公开(公告)日：1998-11-13
申请号：JP10894598
申请日：1998-04-20
Applicant: IBM
Inventor： DALAL HORMAZDYAR M , GAUDENZI GENE JOSEPH , GORRELL REBECCA Y , TAKACS MARK A , TRAVIS JR KENNETH J
Abstract: PROBLEM TO BE SOLVED: To provide a superior direct capacitor attachment by loading a mask so that the opening of the mask exposes the upper face of a high melting point solder ball, making low melting point metallic layer adhere on the high melting point solder ball and forming a capacitor having a low melting point metallic cap. SOLUTION: The high melting point solder ball (solder ball) 18 is formed on the semiconductor moist pad 16 of the multilayer insulating capacitor 10. The solder moist pad 16 is connected to the inner electrodes 11 of the capacitor 10 through a shorting bar 12. The mask 20 having the opening 26 is loaded on the capacitor 10 having a solder ball assembly 14 and the solder ball 18. The uppermost part of the solder ball 18 is exposed and tin 23 is adhered by a solder evaporator. When the solder ball 18 having a tin cap 23 is reflowed, an eutectic alloy 43 is formed on the uppermost part of the solder ball 18 and it can be joined to the circuit 47 of a substrate constituted of copper foil on an organic carrier card 40.
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公开(公告)号：DE68910964D1
公开(公告)日：1994-01-05
申请号：DE68910964
申请日：1989-04-11
Applicant: IBM
Inventor： GAUDENZI GENE JOSEPH
IPC: H03K17/04 , H03K19/013 , H03K19/082 , H03K19/086
Abstract: A circuit includes a set of seven NPN transistors (T1-T7), a Schottky diode (SD), and several resistors. The signal is connected from the input section to the output section directly from the base of a transistor (T2) in the input circuit to the base of the lower output transistor (T3), which (T2) is connected with its collector emitter connections in parallel with the emitter resistor (R3) of the input transistors which receive the input signals to the circuit. Two transistors (T1,T6) are connected to input terminals to provide a possible NOR arrangement although one of them alone can be used if the requirement of the circuit is simply for an inverter circuit. The output transistors comprise a push-pull output section (T3,T4).
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公开(公告)号：IN177313B
公开(公告)日：1996-12-28
申请号：IN628DE1989
申请日：1989-07-13
Applicant: IBM
Inventor： BLAND PATRICK MAURICE , DEAN MARK EDWARD , GAUDENZI GENE JOSEPH , KRAMER KEVIN GERRARD , TEMPEST SUSAN LYNN
IPC: G06F7/00
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Patent Agency Ranking
公开(公告)号：HK79794A
公开(公告)日：1994-08-19
申请号：HK79794
申请日：1994-08-11
Applicant: IBM
Inventor： GAUDENZI GENE JOSEPH
IPC: H03K19/013 , H03K19/082 , H03K17/04 , H03K19/086
Abstract: A circuit includes a set of seven NPN transistors (T1-T7), a Schottky diode (SD), and several resistors. The signal is connected from the input section to the output section directly from the base of a transistor (T2) in the input circuit to the base of the lower output transistor (T3), which (T2) is connected with its collector emitter connections in parallel with the emitter resistor (R3) of the input transistors which receive the input signals to the circuit. Two transistors (T1,T6) are connected to input terminals to provide a possible NOR arrangement although one of them alone can be used if the requirement of the circuit is simply for an inverter circuit. The output transistors comprise a push-pull output section (T3,T4).
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公开(公告)号：DE3879089T2
公开(公告)日：1993-09-16
申请号：DE3879089
申请日：1988-08-16
Applicant: IBM
Inventor： GAUDENZI GENE JOSEPH , TEMPEST SUSAN LYNN
Abstract: A voltage regulator for regulating the voltage at a first node, comprising a first voltage supply; a first node; a first transistor with a control terminal connected to the first node; means for varying the VBE voltage drop of said first transistor in accordance with whether the voltage level of the first voltage supply is above or below a threshold voltage and for continuously sinking current from said first transistor; and means for varying the voltage level at the current-emitting terminal of the first transistor to counteract, in combination with the varying VBE voltage drop, the change in the voltage level of the first voltage supply.
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公开(公告)号：PH25883A
公开(公告)日：1991-12-02
申请号：PH38445
申请日：1989-04-06
Applicant: IBM
Inventor： GAUDENZI GENE JOSEPH
IPC: H03K19/013 , H03K17/04 , H03K19/082 , H03K19/086
Abstract: A circuit includes a set of seven NPN transistors (T1-T7), a Schottky diode (SD), and several resistors. The signal is connected from the input section to the output section directly from the base of a transistor (T2) in the input circuit to the base of the lower output transistor (T3), which (T2) is connected with its collector emitter connections in parallel with the emitter resistor (R3) of the input transistors which receive the input signals to the circuit. Two transistors (T1,T6) are connected to input terminals to provide a possible NOR arrangement although one of them alone can be used if the requirement of the circuit is simply for an inverter circuit. The output transistors comprise a push-pull output section (T3,T4).
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公开(公告)号：SG53104A1
公开(公告)日：1998-09-28
申请号：SG1997003744
申请日：1997-10-14
Applicant: IBM
Inventor： DALAL HORMAZDYAR MINOCHER , FALLON KENNETH MICHAEL , GAUDENZI GENE JOSEPH , MILKOVICH CYNTHIA SUSAN
IPC: H01L21/56 , H01L21/60 , H01L23/498 , H01L23/538 , H05K1/18 , H05K3/00 , H05K3/34
Abstract: A structure and method is disclosed for directly attaching a device or package on flexible organic circuit carriers having low cost and high reliability. IC chips with a new solder interconnect structure, comprised of a layer of pure tin, deposited on the top of high melting Pb-Sn solder balls are employed for joining. These methods, techniques and metallurgical structures enables direct attachment of electronic devices of any complexity to any substrate and to any level of packaging hierarchy. Also, devices or packages having other joining technologies, eg. SMT, BGA, TBGA, etc. could be joined onto the flexible circuit carrier.
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