公开(公告)号：DE69203842T2

公开(公告)日：1996-05-02

申请号：DE69203842

申请日：1992-12-03

Applicant: IBM

Inventor： DERWIN MICHAEL THOMAS ,  WALL WILLIAM ALAN

IPC: G06F12/08

Abstract: A personal computer has a memory system including a write-through cache which is accessible by more than one device. A snoop mechanism includes logic that monitors bus master control signals to determine if a new memory write cycle has been started before a current snoop cycle has finished. If a new cycle has been started, then a corresponding snoop cycle occurs which overlaps the new memory cycle and is pipelined with the previous snoop cycle so that the snooping mechanism does not fall behind the memory write cycles.

公开(公告)号：HUT77024A

公开(公告)日：1998-03-02

申请号：HU9702326

申请日：1995-11-23

Applicant: IBM

Inventor： CRONIN DANIEL RAYMOND III ,  KULIK AMY ,  WALL WILLIAM ALAN

IPC: G06F13/40

Abstract: The PCI/ISA bridge (34) is coupled between the PCI and ISA buses (30,32) in a computer system. A PCI master (42) in the system asserts addresses and address parity information on the PCI bus (30) to initiate a master-slave transaction over the PCI bus. The bus bridge includes logic (60) for comparing the address and address parity information, and generating an address parity error signal when there is an address parity error. - The bridge also includes a PCI slave (40) that receives the address parity error signal, and generates a target-abort signal in response if the PCI slave (40) has already claimed the address by asserting a device select signal. the bridge also includes logic that prevents the target-abort signal from propagating to the PCI bus (30) whenever the logic receives both the address parity error signal and the device select signal. This allows the master to perform a master-abort, and prevents the slave on the bridge from performing a target-abort when there is an address parity error.

公开(公告)号：PL322007A1

公开(公告)日：1998-01-05

申请号：PL32200795

申请日：1995-11-23

Applicant: IBM

Inventor： WALL WILLIAM ALAN ,  KULIK AMY ,  CRONIN DANIEL RAYMOND III

IPC: G06F11/30 ,  G06F11/10 ,  G06F13/36 ,  G06F13/40

Abstract: A peripheral controller interconnect/industry standard architecture (PCI/ISA)bridge is coupled between the PCI and ISA buses in a computer system. A PCI master in the system asserts address and address parity information on the PCI bus to initiate a master-slave transaction over the PCI bus. The bridge includes logic for comparing the address and the address parity information and generating an address parity error signal when there is an address parity error. The bridge also includes a PCI slave that receives the address parity error signal and generates a target-abort signal in response if the PCI slave has already claimed the address by asserting a device select signal. The bridge also includes logic that prevents the target-abort signal from propagating to the PCI bus whenever this logic receives both the address parity error signal and the device select signal. This allows the master to perform a master-abort and prevents the PCI slave on the bridge from performing a target-abort when there is an address parity error.

公开(公告)号：PL320020A1

公开(公告)日：1997-09-01

申请号：PL32002095

申请日：1995-11-23

Applicant: IBM

Inventor： KATZ SAGI ,  WALL WILLIAM ALAN ,  KULIK AMY ,  CRONIN DANIEL RAYMOND III

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.

公开(公告)号：DE69203842D1

公开(公告)日：1995-09-07

申请号：DE69203842

申请日：1992-12-03

Applicant: IBM

Inventor： DERWIN MICHAEL THOMAS ,  WALL WILLIAM ALAN

IPC: G06F12/08

Abstract: A personal computer has a memory system including a write-through cache which is accessible by more than one device. A snoop mechanism includes logic that monitors bus master control signals to determine if a new memory write cycle has been started before a current snoop cycle has finished. If a new cycle has been started, then a corresponding snoop cycle occurs which overlaps the new memory cycle and is pipelined with the previous snoop cycle so that the snooping mechanism does not fall behind the memory write cycles.