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公开(公告)号：PL320020A1
公开(公告)日：1997-09-01
申请号：PL32002095
申请日：1995-11-23
Applicant: IBM
Inventor： KATZ SAGI , WALL WILLIAM ALAN , KULIK AMY , CRONIN DANIEL RAYMOND III
Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.
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公开(公告)号：AT176341T
公开(公告)日：1999-02-15
申请号：AT95937968
申请日：1995-11-23
Applicant: IBM
Inventor： KATZ SAGI , WALL WILLIAM ALAN , KULIK AMY , CRONIN DANIEL RAYMOND III
Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.
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公开(公告)号：HUT76791A
公开(公告)日：1997-11-28
申请号：HU9701248
申请日：1995-11-23
Applicant: IBM
Inventor： CRONIN DANIEL RAYMOND III , KATZ SAGI , KULIK AMY , WALL WILLIAM ALAN
Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.
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Patent Agency Ranking
公开(公告)号：BR9505207A
公开(公告)日：1997-09-16
申请号：BR9505207
申请日：1995-11-17
Applicant: IBM
Inventor： KATZ SAGI , WALL WILLIAM ALAN , KULIK AMY , CRONIN DANIEL R
Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.
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公开(公告)号：DE69507636T2
公开(公告)日：1999-08-05
申请号：DE69507636
申请日：1995-11-23
Applicant: IBM
Inventor： KATZ SAGI , WALL WILLIAM , KULIK AMY , CRONIN DANIEL
Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.
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公开(公告)号：CA2162187A1
公开(公告)日：1996-05-31
申请号：CA2162187
申请日：1995-11-06
Applicant: IBM
Inventor： KATZ SAGI , WALL WILLIAM ALAN , KULIK AMY , CRONIN DANIEL R III
Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.
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公开(公告)号：CZ9701508A3
公开(公告)日：2002-05-15
申请号：CZ150897
申请日：1995-11-23
Applicant: IBM
Inventor： KATZ SAGI , WALL WILLIAM ALAN , KULIK AMY , CRONIN DANIEL RAYMOND
Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.
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公开(公告)号：DE69507636D1
公开(公告)日：1999-03-11
申请号：DE69507636
申请日：1995-11-23
Applicant: IBM
Inventor： KATZ SAGI , WALL WILLIAM , KULIK AMY , CRONIN DANIEL
Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.
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