公开(公告)号：DE69507715D1

公开(公告)日：1999-03-18

申请号：DE69507715

申请日：1995-11-23

Applicant: IBM ,  IBM UK

Inventor： KULIK AMY ,  WALL WILLIAM ,  CRONIN DANIEL

IPC: G06F11/30 ,  G06F11/10 ,  G06F13/36 ,  G06F13/40

Abstract: A peripheral controller interconnect/industry standard architecture (PCI/ISA)bridge is coupled between the PCI and ISA buses in a computer system. A PCI master in the system asserts address and address parity information on the PCI bus to initiate a master-slave transaction over the PCI bus. The bridge includes logic for comparing the address and the address parity information and generating an address parity error signal when there is an address parity error. The bridge also includes a PCI slave that receives the address parity error signal and generates a target-abort signal in response if the PCI slave has already claimed the address by asserting a device select signal. The bridge also includes logic that prevents the target-abort signal from propagating to the PCI bus whenever this logic receives both the address parity error signal and the device select signal. This allows the master to perform a master-abort and prevents the PCI slave on the bridge from performing a target-abort when there is an address parity error.

公开(公告)号：CZ9701508A3

公开(公告)日：2002-05-15

申请号：CZ150897

申请日：1995-11-23

Applicant: IBM

Inventor： KATZ SAGI ,  WALL WILLIAM ALAN ,  KULIK AMY ,  CRONIN DANIEL RAYMOND

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.

公开(公告)号：DE69507636D1

公开(公告)日：1999-03-11

申请号：DE69507636

申请日：1995-11-23

Applicant: IBM

Inventor： KATZ SAGI ,  WALL WILLIAM ,  KULIK AMY ,  CRONIN DANIEL

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.

公开(公告)号：CZ290956B6

公开(公告)日：2002-11-13

申请号：CZ156097

申请日：1995-11-23

Applicant: IBM

Inventor： KULIK AMY ,  WALL WILLIAM ALAN ,  CRONIN DANIEL RAYMOND III

IPC: G06F11/30 ,  G06F11/10 ,  G06F13/36 ,  G06F13/40

Abstract: A peripheral controller interconnect/industry standard architecture (PCI/ISA) bridge chip (34)(hereinafter bridge) is coupled between a first bus (30), preferably the PCI bus a second bus (32), preferably ISA bus (32) in a computer system. A PCI master (42) in the system asserts address and address parity information on the PCI bus (30) to initiate a master-slave transaction over the PCI bus. The bridge (34) includes logic (60) for comparing the address and the address parity information and generating an address parity error signal when there is an address parity error. The bridge (34) also includes a PCI slave (40) that receives the address parity error signal and generates a target-abort signal in response if the PCI slave (40) has already claimed the address by asserting a device select signal. The bridge (34) also includes logic that prevents the target-abort signal from propagating to the PCI bus (30) whenever this logic receives both the address parity error signal and the device select signal. This allows the master to perform a master-abort and prevents the PCI slave (40) on the bridge from performing a target-abort when there is an address parity error.

公开(公告)号：DE69507636T2

公开(公告)日：1999-08-05

申请号：DE69507636

申请日：1995-11-23

Applicant: IBM

Inventor： KATZ SAGI ,  WALL WILLIAM ,  KULIK AMY ,  CRONIN DANIEL

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.

公开(公告)号：CA2162187A1

公开(公告)日：1996-05-31

申请号：CA2162187

申请日：1995-11-06

Applicant: IBM

Inventor： KATZ SAGI ,  WALL WILLIAM ALAN ,  KULIK AMY ,  CRONIN DANIEL R III

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/42 ,  G06F13/14

Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.

公开(公告)号：CZ9701560A3

公开(公告)日：2002-05-15

申请号：CZ156097

申请日：1995-11-23

Applicant: IBM

Inventor： KULIK AMY ,  WALL WILLIAM ALAN ,  CRONIN DANIEL RAYMOND III

IPC: G06F11/30 ,  G06F11/10 ,  G06F13/36 ,  G06F13/40

Abstract: A peripheral controller interconnect/industry standard architecture (PCI/ISA)bridge is coupled between the PCI and ISA buses in a computer system. A PCI master in the system asserts address and address parity information on the PCI bus to initiate a master-slave transaction over the PCI bus. The bridge includes logic for comparing the address and the address parity information and generating an address parity error signal when there is an address parity error. The bridge also includes a PCI slave that receives the address parity error signal and generates a target-abort signal in response if the PCI slave has already claimed the address by asserting a device select signal. The bridge also includes logic that prevents the target-abort signal from propagating to the PCI bus whenever this logic receives both the address parity error signal and the device select signal. This allows the master to perform a master-abort and prevents the PCI slave on the bridge from performing a target-abort when there is an address parity error.

公开(公告)号：AT176341T

公开(公告)日：1999-02-15

申请号：AT95937968

申请日：1995-11-23

Applicant: IBM

Inventor： KATZ SAGI ,  WALL WILLIAM ALAN ,  KULIK AMY ,  CRONIN DANIEL RAYMOND III

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.

公开(公告)号：BR9505208A

公开(公告)日：1997-09-16

申请号：BR9505208

申请日：1995-11-17

Applicant: IBM

Inventor： KULIK AMY ,  WALL WILLIAM ALAN ,  CRONIN DANIEL R

IPC: G06F11/30 ,  G06F11/10 ,  G06F13/36 ,  G06F13/40

Abstract: A peripheral controller interconnect/industry standard architecture (PCI/ISA)bridge is coupled between the PCI and ISA buses in a computer system. A PCI master in the system asserts address and address parity information on the PCI bus to initiate a master-slave transaction over the PCI bus. The bridge includes logic for comparing the address and the address parity information and generating an address parity error signal when there is an address parity error. The bridge also includes a PCI slave that receives the address parity error signal and generates a target-abort signal in response if the PCI slave has already claimed the address by asserting a device select signal. The bridge also includes logic that prevents the target-abort signal from propagating to the PCI bus whenever this logic receives both the address parity error signal and the device select signal. This allows the master to perform a master-abort and prevents the PCI slave on the bridge from performing a target-abort when there is an address parity error.

公开(公告)号：CA2160500A1

公开(公告)日：1996-05-31

申请号：CA2160500

申请日：1995-10-13

Applicant: IBM

Inventor： KULIK AMY ,  WALL WILLIAM ALAN ,  CRONIN DANIEL R III

IPC: G06F11/30 ,  G06F11/10 ,  G06F13/36 ,  G06F13/40 ,  G06F13/14

Abstract: A peripheral controller interconnect/industry standard architecture (PCI/ISA)bridge is coupled between the PCI and ISA buses in a computer system. A PCI master in the system asserts address and address parity information on the PCI bus to initiate a master-slave transaction over the PCI bus. The bridge includes logic for comparing the address and the address parity information and generating an address parity error signal when there is an address parity error. The bridge also includes a PCI slave that receives the address parity error signal and generates a target-abort signal in response if the PCI slave has already claimed the address by asserting a device select signal. The bridge also includes logic that prevents the target-abort signal from propagating to the PCI bus whenever this logic receives both the address parity error signal and the device select signal. This allows the master to perform a master-abort and prevents the PCI slave on the bridge from performing a target-abort when there is an address parity error.