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公开(公告)号：FR2336769A1
公开(公告)日：1977-07-22
申请号：FR7636144
申请日：1976-11-24
Applicant: IBM
Inventor： BRYANT LOUIS R , PEDERSEN RAYMOND J , WEINBERGER ARNOLD
Abstract: A digital LRU network in which a use value in a chronology register always appears to be increasing; it is incremented for each access to a different data block currently represented in an active LRU array and this use value is copied into an index for that block in an active use-value array. Special circuits are provided to maintain the appearance of continuously increasing use values. At the start of each array search, the special circuits check the chronology register to determine if its use value is nearing its highest registerable value by testing its two high order bits for 1's. If so, the chronology register is set to 100...0, which is higher than any use value in the active array, after the use values in the active array are shifted one bit position to the right by writing them into corresponding positions in another array, which then becomes the active array. The right shift drops the low-order bit in the use values and sets the high-order bit to zero. The right shift increases the range of use values that can subsequently be set into the active array without affecting the stored relationships among the existing use values, and enables the incrementing of use values to continue. The second array is used to permit overlap of the read cycle of one array with the write cycle of the other array.
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公开(公告)号：CA893370A
公开(公告)日：1972-02-15
申请号：CA893370D
Applicant: IBM
Inventor： BIDWELL ALEXANDER W , WEINBERGER ARNOLD
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公开(公告)号：DE2914723A1
公开(公告)日：1980-08-28
申请号：DE2914723
申请日：1979-04-11
Applicant: IBM
Inventor： WEINBERGER ARNOLD
Abstract: The adder has a PLA circuit whose AND-matrix decoder is coupled on the input sie to two inputs and four outputs and whose OR-matrix has exclusive-OR latch circuits with two inputs on its output side. A specif. logical operational is performed by the AND and OR matrices to prod. sum bits. An intermediate sum at a given bit position is determined according to a specified logical relationship. The output carry bit is determined by a specif. logical relationship. The intermediate sum needed to calculate higher sum bits is also determined by a given logical relationship.
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公开(公告)号：FR2413713A1
公开(公告)日：1979-07-27
申请号：FR7836053
申请日：1978-12-05
Applicant: IBM
Inventor： GRICE DONAL G , JOHNSON DAVID F , WEINBERGER ARNOLD
Abstract: This specification discloses a multi digit binary adder embodied in programmable logic arrays (PLAs). The particular programmable logic array used here has a separate two bit decoder for receiving each like order pairs of digits Ai, Bi of two n digit binary numbers A0, A1....An-1 and B0, B1....Bn-1 plus a carry Cin. The decoders generate an output signal called a min term on a different line for each of the four possible combinations AiBi, AiBi, AiBi and AiBi of the true and complement of each pair. The min terms from the decoders are fed to an array called the product term generator or AND array which generates product terms FP=F0(A0,B0) f1(A1,B1)....fn-1(An-1, Bn-1) fn(Cin) The product terms are fed to a second array called a sum of product term generator or OR array that sums product terms fp. A series of latches is last in the sequence of logic elements making up the PLA. These latches each perform an AND function to generate a sum bit Si that is an AND of two functions supplied by the OR array to the inputs of the latches to generate a sum S0, S1....Sn-1 plus a carry Cout for the adder at the output of the PLA. The adder is optimized for a PLA with latches that perform an AND function.
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公开(公告)号：DE2656546A1
公开(公告)日：1977-07-07
申请号：DE2656546
申请日：1976-12-14
Applicant: IBM
Inventor： BRYANT LOUIS RONALD , PEDERSEN RAYMOND JAMES , WEINBERGER ARNOLD
Abstract: A digital LRU network in which a use value in a chronology register always appears to be increasing; it is incremented for each access to a different data block currently represented in an active LRU array and this use value is copied into an index for that block in an active use-value array. Special circuits are provided to maintain the appearance of continuously increasing use values. At the start of each array search, the special circuits check the chronology register to determine if its use value is nearing its highest registerable value by testing its two high order bits for 1's. If so, the chronology register is set to 100...0, which is higher than any use value in the active array, after the use values in the active array are shifted one bit position to the right by writing them into corresponding positions in another array, which then becomes the active array. The right shift drops the low-order bit in the use values and sets the high-order bit to zero. The right shift increases the range of use values that can subsequently be set into the active array without affecting the stored relationships among the existing use values, and enables the incrementing of use values to continue. The second array is used to permit overlap of the read cycle of one array with the write cycle of the other array.
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Patent Agency Ranking
公开(公告)号：FR2313712A1
公开(公告)日：1976-12-31
申请号：FR7610902
申请日：1976-04-08
Applicant: IBM
Inventor： WEINBERGER ARNOLD
Abstract: Logic circuits in an adder for use in data processing for the detection of a sum of all ZEROES together with the mathematics upon which the circuits are based. Circuits and mathematics are also disclosed for a detection of a sum of all digits equal to the radix less one. Each of these detected sum conditions are produced prior to or at least concurrently with the production of the sum itself.
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公开(公告)号：DE2527062A1
公开(公告)日：1976-01-15
申请号：DE2527062
申请日：1975-06-18
Applicant: IBM
Inventor： MESSINA BENEDICTO UMBERTO , WEINBERGER ARNOLD
Abstract: 1468783 Digital data storage systems INTERNATIONAL BUSINESS MACHINES CORP 4 April 1975 [27 June 1974] 13815/75 Heading G4A A memory system in which the number and sizes of memory hardware modules 12 are variable includes means for applying at least part of a word address 10 to each module present, and writable control means 14 responsive to some of the bits of the address to apply to the modules access-enabling signals generated as a function of said bits and of the current contents of the control means whereby module addressing can be adjusted by rewriting the writable control means. As disclosed, ten bits of the address go to the writable control means, and to each module goes a subset of these bits together with the remaining bits of the address and a select output from the writable control means. The writable control means has a notional matrix of stored bits, having 64 columns and 32 rows. Five bits of the address are decoded to select 1 of 32 columns, and five more address bits are decoded to select 1 of the other 32 columns. This reads out 2 bits for each row, these two bits being ORed together to form a row signal which, if O, selects a corresponding one of the memory modules mentioned. Some row signals may not be in use (depending on the number of modules), and two row signals may be ANDed together. The 32 x 64 bit notional matrix may be formed of 4 chips, each storing 16 x 32 bits and having its own decoder. The correspondence between addresses received and locations in the set of memory modules depends on the bit values stored in the writable control means 32 x 64 bit notional matrix. Selection of a given module may be prevented completely by loading all 1 bits into one half of the corresponding row. If part of a row is defective, its use in selection can be prevented by loading all 1 bits into the good half of the row. For added reliability, the same information may be stored in two rows and both used to select the corresponding module. To change the information stored in the 32 x 64 bit notional matrix, a 6-bit address is used to select a column and a 5-bit address is used to select a row. One bit from each of these addresses are combined to select one of the 4 chips, and the other 5 bits of the column address select a column within the chip, this column being read-out, and then re-written after a new bit value has been supplied to a bit position in the column selected by the other 4 bits of the row address. Thus the information is changed a bit at a time, selection being row by row. The stored information can also be read-out similarly without rewriting.
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公开(公告)号：DE2259725A1
公开(公告)日：1973-07-05
申请号：DE2259725
申请日：1972-12-06
Applicant: IBM
Inventor： WEINBERGER ARNOLD
IPC: G06F7/02 , G06F17/30 , G11C11/56 , G11C15/04 , H03K19/173 , H03K19/177 , G11C27/00
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公开(公告)号：CA1059643A
公开(公告)日：1979-07-31
申请号：CA268655
申请日：1976-12-23
Applicant: IBM
Inventor： BRYANT LOUIS R , PEDERSEN RAYMOND J , WEINBERGER ARNOLD
Abstract: A CIRCUIT FOR IMPLEMENTING A MODIFIED LRU REPLACEMENT ALGORITHM FOR A CACHE The invention operates with a storage hierarchy buffer such as a cache, with an LRU network which utilizes two array memory chips, array selection and addressing controls, chronology controls, next LRU addressing circuits, and mode controls for controlling the different types of operations needed by the LRU network. Each time a different block is accessed in the cache, a next use value is generated in a chronology register in the chronology controls, and the new use value is written into the active one of the arrays at a position which corresponds to the position of the block to be replaced in the cache. An LRU determination is made when a cache miss occurs by making a search of the active array to find the position of the block with the lowest use value, which block position is thus determined to be the LRU. This LRU block address is then stored in the next LRU addressing circuits for use by the next block replacement in the cache, i.e. next miss.
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公开(公告)号：FR2326081A1
公开(公告)日：1977-04-22
申请号：FR7626313
申请日：1976-08-25
Applicant: IBM
Inventor： ARPS RONALD B , BAHL LALIT R , WEINBERGER ARNOLD
Abstract: An apparatus is disclosed for compressing a p x q image array of two-valued (black/white) sample points. The image array points are serially applied to the apparatus in consecutive raster scan lines. In response, the apparatus simultaneously forms two matrices respectively representing a high order p x q predictive error array and a p x q array of location events (such as the raster leading edges of all objects in the image). Improved compression is achieved by selecting between the more compression efficient of two methods for encoding the position of errors in the prediction error array. These alternative methods are conventional run-length coding and a novel form of reference encoding, used selectively but to significant advantage. Thus, a run-length compression codeword is formed from the count C of non-errors between consecutive errors (in response to the occurrence of each error in the jth bit position of the ith scan line of the predictive error array) upon either C T and there being no occurrence of a line difference encoding for the error (where i, j, C and T have positive integers). A line difference codeword with difference value v is generated upon the joint event of C>T and either the single or multiple occurrence of location events in the ith-1 scan line of the location event array within the bit position range of B
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