公开(公告)号：US3475621A

公开(公告)日：1969-10-28

申请号：US3475621D

申请日：1967-03-23

Applicant: IBM

Inventor： WEINBERGER ARNOLD

IPC: H01L27/02 ,  H01L27/088 ,  H01L27/112 ,  H01L27/118 ,  H03K19/0944 ,  H03K19/34

CPC classification number: H03K19/09441 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/112 ,  H01L27/11803

公开(公告)号：US3548386A

公开(公告)日：1970-12-15

申请号：US3548386D

申请日：1968-07-15

Applicant: IBM

Inventor： BIDWELL ALEXANDER W ,  WEINBERGER ARNOLD

IPC: G11C15/04 ,  G11C11/40

CPC classification number: G11C15/04

公开(公告)号：US3603776A

公开(公告)日：1971-09-07

申请号：US3603776D

申请日：1969-01-15

Applicant: IBM

Inventor： WEINBERGER ARNOLD

IPC: G06F7/50 ,  G06F7/509 ,  G06F7/60 ,  G06F5/02

CPC classification number: G06F7/509 ,  G06F7/607 ,  G06F2207/4818

Abstract: Disclosed are counters for counting inputs in terms of a fewer number of outputs. The counters are useful in batch adders for simultaneously adding a plurality of multibit numbers. The counters include first and second binary threshold function generators which each receive a different group of inputs. The generators are in parallel with respect to the inputs and each generates a plurality of binary threshold functions. The binary threshold functions are selectively combined in first, second and third threshold combining circuits to form the counter outputs. The combining circuits are placed in parallel and each circuit logically combines one or more threshold function inputs derived from the function generators.

公开(公告)号：US3593317A

公开(公告)日：1971-07-13

申请号：US3593317D

申请日：1969-12-30

Applicant: IBM

Inventor： FLEISHER HAROLD ,  WEINBERGER ARNOLD ,  WINKLER VAUGHN D

IPC: H03K19/177 ,  G06C15/00

CPC classification number: H03K19/177

Abstract: An improved method and means to implement a logic function F of N variables by partitioning the logic operation in a plurality of generalized logic matrices. It is first mathematically demonstrated that a function F of N variables may be expanded into subfunctions of a lesser number of variables. These subfunctions may be logically implemented individually and then logically combined so as to produce the desired function of N variables with a concomitant savings in logic circuitry over that required if the functions were directly implemented. The means used to implement the logic function F are a plurality of generalized logic matrices, each of which comprises a plurality of logic gates arranged in columns and rows, an input decoder for accepting the input variables, and a storage register for varying the functions generated at the output of the matrix. These matrices are arranged in cascade so that, as the function F is constructed from the several subfunctions, additional variables are inserted at each matrix stage until the function F of N variables is fully generated.

公开(公告)号：US3644906A

公开(公告)日：1972-02-22

申请号：US3644906D

申请日：1969-12-24

Applicant: IBM

Inventor： WEINBERGER ARNOLD

IPC: G11C15/00 ,  G06F15/78 ,  G06F17/30 ,  G11C15/04 ,  G11C5/02

CPC classification number: G06F17/30982 ,  G06F15/7839

Abstract: A memory is disclosed in which words are located by both associative and nonassociative addressing. The nonassociative portion of the address defines a general category for the word being searched and a corresponding portion of the memory. The associative portion of the address is searched within the addressed portion of the memory without regard to the actual memory location. Conventional nonassociative storage cell arrays are arranged to be addressed as an associative memory of threestate storage cells.

公开(公告)号：US3629565A

公开(公告)日：1971-12-21

申请号：US3629565D

申请日：1970-02-13

Applicant: IBM

Inventor： SCHMOOKLER MARTIN S ,  WEINBERGER ARNOLD

IPC: G06F7/494 ,  G06F7/50

CPC classification number: G06F7/494 ,  G06F2207/4924

Abstract: An improved method and logic system for adding two decimal numbers which are coded in a four-bit binary form. The method includes generating a propagate carry signal Pi for each of the four bits which is the OR function of the bit inputs, generating a generate carry signal Gi for each of the four bits which is the AND function of the bit inputs, and generating a binary carry C1 for the first bit. The decimal carry for the addition is then generated by a novel carry look-ahead technique by employing these signals: Pi, Gi, and the binary carry C1. The binary coded decimal bit signals representative of the decimal sum are also generated directly from these signals and, hence, the adder differs from prior art decimal adders which first performed binary addition in each bit and then added 6 to these binary sums whenever a decimal carry occurred so as to produce corrected binary signals representative of the coded decimal number. Several systems are disclosed employing this method and include a four-logic level, two-digit decimal adder, a three-logic level, two-digit decimal adder; and a six-logic level, eight-digit decimal adder. The six-logic level, eight-digit decimal adder combines concepts of the disclosed novel method for implementing decimal carries, as well as conventional group carry techniques used in parallel binary adders.

公开(公告)号：US3466611A

公开(公告)日：1969-09-09

申请号：US3466611D

申请日：1966-12-28

Applicant: IBM

Inventor： WEINBERGER ARNOLD

IPC: G11C11/06 ,  G11B13/00 ,  G06F1/00 ,  G06F7/00

CPC classification number: G11C11/06042

公开(公告)号：DE2855947A1

公开(公告)日：1979-07-05

申请号：DE2855947

申请日：1978-12-23

Applicant: IBM

Inventor： WEINBERGER ARNOLD

IPC: G06F7/50 ,  G06F7/505 ,  G06F7/508

公开(公告)号：CA1032274A

公开(公告)日：1978-05-30

申请号：CA225985

申请日：1975-04-29

Applicant: IBM

Inventor： MESSINA BENEDICTO U ,  WEINBERGER ARNOLD

IPC: G11C15/00 ,  G06F12/06 ,  G11C15/04 ,  G11C9/08

Abstract: 1468783 Digital data storage systems INTERNATIONAL BUSINESS MACHINES CORP 4 April 1975 [27 June 1974] 13815/75 Heading G4A A memory system in which the number and sizes of memory hardware modules 12 are variable includes means for applying at least part of a word address 10 to each module present, and writable control means 14 responsive to some of the bits of the address to apply to the modules access-enabling signals generated as a function of said bits and of the current contents of the control means whereby module addressing can be adjusted by rewriting the writable control means. As disclosed, ten bits of the address go to the writable control means, and to each module goes a subset of these bits together with the remaining bits of the address and a select output from the writable control means. The writable control means has a notional matrix of stored bits, having 64 columns and 32 rows. Five bits of the address are decoded to select 1 of 32 columns, and five more address bits are decoded to select 1 of the other 32 columns. This reads out 2 bits for each row, these two bits being ORed together to form a row signal which, if O, selects a corresponding one of the memory modules mentioned. Some row signals may not be in use (depending on the number of modules), and two row signals may be ANDed together. The 32 x 64 bit notional matrix may be formed of 4 chips, each storing 16 x 32 bits and having its own decoder. The correspondence between addresses received and locations in the set of memory modules depends on the bit values stored in the writable control means 32 x 64 bit notional matrix. Selection of a given module may be prevented completely by loading all 1 bits into one half of the corresponding row. If part of a row is defective, its use in selection can be prevented by loading all 1 bits into the good half of the row. For added reliability, the same information may be stored in two rows and both used to select the corresponding module. To change the information stored in the 32 x 64 bit notional matrix, a 6-bit address is used to select a column and a 5-bit address is used to select a row. One bit from each of these addresses are combined to select one of the 4 chips, and the other 5 bits of the column address select a column within the chip, this column being read-out, and then re-written after a new bit value has been supplied to a bit position in the column selected by the other 4 bits of the row address. Thus the information is changed a bit at a time, selection being row by row. The stored information can also be read-out similarly without rewriting.

公开(公告)号：FR2342587A1

公开(公告)日：1977-09-23

申请号：FR7700648

申请日：1977-01-05

Applicant: IBM

Inventor： WEINBERGER ARNOLD

IPC: H03M7/04 ,  G06F7/76 ,  G06F12/04 ,  H03M7/00 ,  H03M7/08 ,  H03K13/243 ,  G06F5/00

Abstract: Disclosed is a decoder which receives a number of coded binary-weighted input signals and which provides, on a plurality of output signal lines, a threshold related to the coded value of the input signals. The threshold is defined at the output as a consecutive sequence of output signal lines having a binary 0 value on one side of the threshold, and a consecutive sequence of output signals on the other side of the threshold having a binary value of 1. In one embodiment, a single level of binary logic receives n input signals and produces a threshold on m = 2n-1 output signal lines. A second embodiment receives n input signals which are divided into groups of signals, each group of which is applied to an intermediate threshold generator, the outputs of which are combined in a final level to provide m output signals. A further embodiment of the threshold decoder receives two groups of input signals which are combined in a first level of intermediate threshold generators, the outputs of which are then combined in a final stage which may produce more than one threshold on the output signal lines. Another further embodiment of the threshold decoder discloses a plurality of groups of input signal lines, combined in a plurality of intermediate threshold generators, the outputs of which are combined in a final level of logic to produce, selectively, a like plurality of thresholds on the output signal lines.