公开(公告)号：CA1059643A

公开(公告)日：1979-07-31

申请号：CA268655

申请日：1976-12-23

Applicant: IBM

Inventor： BRYANT LOUIS R ,  PEDERSEN RAYMOND J ,  WEINBERGER ARNOLD

IPC: G06F12/12 ,  G06F7/10 ,  G11C9/06

Abstract: A CIRCUIT FOR IMPLEMENTING A MODIFIED LRU REPLACEMENT ALGORITHM FOR A CACHE The invention operates with a storage hierarchy buffer such as a cache, with an LRU network which utilizes two array memory chips, array selection and addressing controls, chronology controls, next LRU addressing circuits, and mode controls for controlling the different types of operations needed by the LRU network. Each time a different block is accessed in the cache, a next use value is generated in a chronology register in the chronology controls, and the new use value is written into the active one of the arrays at a position which corresponds to the position of the block to be replaced in the cache. An LRU determination is made when a cache miss occurs by making a search of the active array to find the position of the block with the lowest use value, which block position is thus determined to be the LRU. This LRU block address is then stored in the next LRU addressing circuits for use by the next block replacement in the cache, i.e. next miss.

公开(公告)号：CA2060555A1

公开(公告)日：1992-10-25

申请号：CA2060555

申请日：1992-02-03

Applicant: IBM

Inventor： BULLIONS ROBERT J III ,  HILL RONALD F ,  NADAS STEPHEN J ,  PEDERSEN RAYMOND J

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/318 ,  G06F9/46 ,  G06F15/16

Abstract: P09-91-013 SYSTEM AND METHOD FOR DRAINING AN INSTRUCTION PIPELINE The present invention comprises a system and method for selectively draining an instruction pipeline. In one embodiment, the invention is implemented in the context of pipelined processor having an interpretive storage and multiple execution units. In the described system, the instructions held in the interpretive storage are referred to as "milli-instructions" and the interpretive execution mode is referred to as "milli-mode". Additional hardware controlled instructions (private milli-mode only instructions) are added to provide control functions or to improve performance. These private milli-mode instructions augment the architected instruction set. Milli-mode routines can intermingle the milli-mode only instructions with architected instructions to implement complex functions. In order to provide an enhanced level of flexibility and efficiency, the above-described embodiment includes a milli-instruction that causes the pipeline to drain. This milli-instruction, called DRAIN INSTRUCTION PIPELINE (DIP) allows greater selectivity by the coder over (1) when to drain the pipeline and (2) what type of pipeline drain to perform. In the preferred embodiment, the DIP instruction enables the coder to cause the system to suspend decoding until a selected event occurs. Specifically, the instruction includes options to suspend decoding until a selected one of the following events has occurred: all conceptually previous macro instructions have completed; all conceptually previous milli-code instructions have completed; all conceptually previous instructions have completed; all store requests have reached the point where no exceptions will occur, but the actual store may not have completed; all conceptually previous stores from all conceptually previous units-of-operation have completed (serialize); or invalidate instruction buffers and fetch the next sequential macro-instructions.

公开(公告)号：CA2058392A1

公开(公告)日：1992-07-17

申请号：CA2058392

申请日：1991-12-23

Applicant: IBM

Inventor： BERSTIS VIKTORS ,  LIPTAY JOHN S ,  PEDERSEN RAYMOND J

IPC: G06F9/34 ,  G06F9/355 ,  G06F9/38

Abstract: P09-90-014 STORAGE OPERAND MANAGEMENT In a computer system having a system memory, m architected logical register and an array of n physical registers, where n is greater than m, a method of managing storage operands including the steps of: detecting the decoding of an instruction having at least one field specifying a storage operand; identifying an available one of the physical registers; fetching the storage operand from the system memory; loading the storage operand into the available one of the physical registers; and executing the instruction, using the storage operand stored in the one of the physical registers.

公开(公告)号：CA1180454A

公开(公告)日：1985-01-02

申请号：CA399155

申请日：1982-03-23

Applicant: IBM

Inventor： JOHNSON LANCE H ,  KISELAK JOHN A II ,  NADARZYNSKI EDWARD A ,  PEDERSEN RAYMOND J

IPC: G06F9/22 ,  G06F9/06 ,  G06F9/26 ,  G06F11/20

Abstract: A microinstruction control storage mechanism includes a read-only store (ROS), writeable control store (WCS), first cycle control store, and a reserved portion of main storage in a data processing system. As required, blocks of microinstructions are paged into the WCS from the main storage. An array of single-bit storage devices, accessed by microinstruction addresses utilized to access microinstructions from the ROS, signal the existence of a faulty microinstruction from the ROS as determined by maintenance or design personnel. In response to a halt signal from an accessed single-bit storage device, an address substitution mechanism creates a microinstruction address which identifies a main storage location and may have to be used to initiate transfer of a block of microinstructions from main storage to the WCS to provide access to a particular substitute microinstruction for the faulty microinstruction.

公开(公告)号：FR2336769A1

公开(公告)日：1977-07-22

申请号：FR7636144

申请日：1976-11-24

Applicant: IBM

Inventor： BRYANT LOUIS R ,  PEDERSEN RAYMOND J ,  WEINBERGER ARNOLD

IPC: G06F12/12 ,  G11C8/00

Abstract: A digital LRU network in which a use value in a chronology register always appears to be increasing; it is incremented for each access to a different data block currently represented in an active LRU array and this use value is copied into an index for that block in an active use-value array. Special circuits are provided to maintain the appearance of continuously increasing use values. At the start of each array search, the special circuits check the chronology register to determine if its use value is nearing its highest registerable value by testing its two high order bits for 1's. If so, the chronology register is set to 100...0, which is higher than any use value in the active array, after the use values in the active array are shifted one bit position to the right by writing them into corresponding positions in another array, which then becomes the active array. The right shift drops the low-order bit in the use values and sets the high-order bit to zero. The right shift increases the range of use values that can subsequently be set into the active array without affecting the stored relationships among the existing use values, and enables the incrementing of use values to continue. The second array is used to permit overlap of the read cycle of one array with the write cycle of the other array.